Programming memristor arrays with arbitrarily high precision for analog computing.

In-memory computing represents an effective method for modeling complex physical systems that are typically challenging for conventional computing architectures but has been hindered by issues such as reading noise and writing variability that restrict scalability, accuracy, and precision in high-performance computations. We propose and demonstrate a circuit architecture and programming protocol that converts the analog computing result to digital at the last step and enables low-precision analog devices to perform high-precision computing. We use a weighted sum of multiple devices to represent one number, in which subsequently programmed devices are used to compensate for preceding programming errors. With a memristor system-on-chip, we experimentally demonstrate high-precision solutions for multiple scientific computing tasks while maintaining a substantial power efficiency advantage over conventional digital approaches.

Thousands of conductance levels in memristors integrated on CMOS.

Neural networks based on memristive devices1-3 have the ability to improve throughput and energy efficiency for machine learning4,5 and artificial intelligence6, especially in edge applications7-21. Because training a neural network model from scratch is costly in terms of hardware resources, time and energy, it is impractical to do it individually on billions of memristive neural networks distributed at the edge. A practical approach would be to download the synaptic weights obtained from the cloud training and program them directly into memristors for the commercialization of edge applications. Some post-tuning in memristor conductance could be done afterwards or during applications to adapt to specific situations. Therefore, in neural network applications, memristors require high-precision programmability to guarantee uniform and accurate performance across a large number of memristive networks22-28. This requires many distinguishable conductance levels on each memristive device, not only laboratory-made devices but also devices fabricated in factories. Analog memristors with many conductance states also benefit other applications, such as neural network training, scientific computing and even 'mortal computing'25,29,30. Here we report 2,048 conductance levels achieved with memristors in fully integrated chips with 256 × 256 memristor arrays monolithically integrated on complementary metal-oxide-semiconductor (CMOS) circuits in a commercial foundry. We have identified the underlying physics that previously limited the number of conductance levels that could be achieved in memristors and developed electrical operation protocols to avoid such limitations. These results provide insights into the fundamental understanding of the microscopic picture of memristive switching as well as approaches to enable high-precision memristors for various applications. Fig. 1 HIGH-PRECISION MEMRISTOR FOR NEUROMORPHIC COMPUTING.: a, Proposed scheme of the large-scale application of memristive neural networks for edge computing. Neural network training is performed in the cloud. The obtained weights are downloaded and accurately programmed into a massive number of memristor arrays distributed at the edge, which imposes high-precision requirements on memristive devices. b, An eight-inch wafer with memristors fabricated by a commercial semiconductor manufacturer. c, High-resolution transmission electron microscopy image of the cross-section view of a memristor. Pt and Ta serve as the bottom electrode (BE) and top electrode (TE), respectively. Scale bars, 1 µm and 100 nm (inset). d, Magnification of the memristor material stack. Scale bar, 5 nm. e, As-programmed (blue) and after-denoising (red) currents of a memristor are read by a constant voltage (0.2 V). The denoising process eliminated the large-amplitude RTN observed in the as-programmed state (see Methods). f, Magnification of three nearest-neighbour states after denoising. The current of each state was read by a constant voltage (0.2 V). No large-amplitude RTN was observed, and all of the states can be clearly distinguished. g, An individual memristor on the chip was tuned into 2,048 resistance levels by high-resolution off-chip driving circuitry, and each resistance level was read by a d.c. voltage sweeping from 0 to 0.2 V. The target resistance was set from 50 µS to 4,144 µS with a 2-µS interval between neighbouring levels. All readings at 0.2 V are less than 1 µS from the target conductance. Bottom inset, magnification of the resistance levels. Top inset, experimental results of an entire 256 × 256 array programmed by its 6-bit on-chip circuitry into 64 32 × 32 blocks, and each block is programmed into one of the 64 conductance levels. Each of the 256 × 256 memristors has been previously switched over one million cycles, demonstrating the high endurance and robustness of the devices.

Memristive Field-Programmable Analog Arrays for Analog Computing.

The increasing interests in analog computing nowadays call for multipurpose analog computing platforms with reconfigurability. The advancement of analog computing, enabled by novel electronic elements like memristors, has shown its potential to sustain the exponential growth of computing demand in the new era of analog data deluge. Here, a platform of a memristive field-programmable analog array (memFPAA) is experimentally demonstrated with memristive devices serving as a variety of core analog elements and CMOS components as peripheral circuits. The memFPAA is reconfigured to implement a first-order band pass filter, an audio equalizer, and an acoustic mixed frequency classifier, as application examples. The memFPAA, featured with programmable analog memristors, memristive routing networks, and memristive vector-matrix multipliers, opens opportunities for fast prototyping analog designs as well as efficient analog applications in signal processing and neuromorphic computing.

Three-Dimensional Nanoscale Flexible Memristor Networks with Ultralow Power for Information Transmission and Processing Application.

To construct an artificial intelligence system with high efficient information integration and computing capability like the human brain, it is necessary to realize the biological neurotransmission and information processing in artificial neural network (ANN), rather than a single electronic synapse as most reports. Because the power consumption of single synaptic event is ∼10 fJ in biology, designing an intelligent memristors-based 3D ANN with energy consumption lower than femtojoule-level (e.g., attojoule-level) and faster operating speed than millisecond-level makes it possible for constructing a higher energy efficient and higher speed computing system than the human brain. In this paper, a flexible 3D crossbar memristor array is presented, exhibiting the multilevel information transmission functionality with the power consumption of 4.28 aJ and the response speed of 50 ns per synaptic event. This work is a significant step toward the development of an ultrahigh efficient and ultrahigh-speed wearable 3D neuromorphic computing system.

An artificial spiking afferent nerve based on Mott memristors for neurorobotics.

Neuromorphic computing based on spikes offers great potential in highly efficient computing paradigms. Recently, several hardware implementations of spiking neural networks based on traditional complementary metal-oxide semiconductor technology or memristors have been developed. However, an interface (called an afferent nerve in biology) with the environment, which converts the analog signal from sensors into spikes in spiking neural networks, is yet to be demonstrated. Here we propose and experimentally demonstrate an artificial spiking afferent nerve based on highly reliable NbOx Mott memristors for the first time. The spiking frequency of the afferent nerve is proportional to the stimuli intensity before encountering noxiously high stimuli, and then starts to reduce the spiking frequency at an inflection point. Using this afferent nerve, we further build a power-free spiking mechanoreceptor system with a passive piezoelectric device as the tactile sensor. The experimental results indicate that our afferent nerve is promising for constructing self-aware neurorobotics in the future.

Bridging Biological and Artificial Neural Networks with Emerging Neuromorphic Devices: Fundamentals, Progress, and Challenges.

As the research on artificial intelligence booms, there is broad interest in brain-inspired computing using novel neuromorphic devices. The potential of various emerging materials and devices for neuromorphic computing has attracted extensive research efforts, leading to a large number of publications. Going forward, in order to better emulate the brain's functions, its relevant fundamentals, working mechanisms, and resultant behaviors need to be re-visited, better understood, and connected to electronics. A systematic overview of biological and artificial neural systems is given, along with their related critical mechanisms. Recent progress in neuromorphic devices is reviewed and, more importantly, the existing challenges are highlighted to hopefully shed light on future research directions.

Capacitive neural network with neuro-transistors.

Experimental demonstration of resistive neural networks has been the recent focus of hardware implementation of neuromorphic computing. Capacitive neural networks, which call for novel building blocks, provide an alternative physical embodiment of neural networks featuring a lower static power and a better emulation of neural functionalities. Here, we develop neuro-transistors by integrating dynamic pseudo-memcapacitors as the gates of transistors to produce electronic analogs of the soma and axon of a neuron, with "leaky integrate-and-fire" dynamics augmented by a signal gain on the output. Paired with non-volatile pseudo-memcapacitive synapses, a Hebbian-like learning mechanism is implemented in a capacitive switching network, leading to the observed associative learning. A prototypical fully integrated capacitive neural network is built and used to classify inputs of signals.

A novel true random number generator based on a stochastic diffusive memristor.

The intrinsic variability of switching behavior in memristors has been a major obstacle to their adoption as the next generation of universal memory. On the other hand, this natural stochasticity can be valuable for hardware security applications. Here we propose and demonstrate a novel true random number generator utilizing the stochastic delay time of threshold switching in a Ag:SiO2 diffusive memristor, which exhibits evident advantages in scalability, circuit complexity, and power consumption. The random bits generated by the diffusive memristor true random number generator pass all 15 NIST randomness tests without any post-processing, a first for memristive-switching true random number generators. Based on nanoparticle dynamic simulation and analytical estimates, we attribute the stochasticity in delay time to the probabilistic process by which Ag particles detach from a Ag reservoir. This work paves the way for memristors in hardware security applications for the era of the Internet of Things.Memristors can switch between high and low electrical-resistance states, but the switching behaviour can be unpredictable. Here, the authors harness this unpredictability to develop a memristor-based true random number generator that uses the stochastic delay time of threshold switching.

Anatomy of Ag/Hafnia-Based Selectors with 1010 Nonlinearity.

A novel Ag/oxide-based threshold switching device with attractive features including ≈1010 nonlinearity is developed. High-resolution transmission electron microscopic analysis of the nanoscale crosspoint device suggests that elongation of an Ag nanoparticle under voltage bias followed by spontaneous reformation of a more spherical shape after power off is responsible for the observed threshold switching.