Cryogenic Memory Architecture Integrating Spin Hall Effect based Magnetic Memory and Superconductive Cryotron Devices.

One of the most challenging obstacles to realizing exascale computing is minimizing the energy consumption of L2 cache, main memory, and interconnects to that memory. For promising cryogenic computing schemes utilizing Josephson junction superconducting logic, this obstacle is exacerbated by the cryogenic system requirements that expose the technology's lack of high-density, high-speed and power-efficient memory. Here we demonstrate an array of cryogenic memory cells consisting of a non-volatile three-terminal magnetic tunnel junction element driven by the spin Hall effect, combined with a superconducting heater-cryotron bit-select element. The write energy of these memory elements is roughly 8 pJ with a bit-select element, designed to achieve a minimum overhead power consumption of about 30%. Individual magnetic memory cells measured at 4 K show reliable switching with write error rates below 10-6, and a 4 × 4 array can be fully addressed with bit select error rates of 10-6. This demonstration is a first step towards a full cryogenic memory architecture targeting energy and performance specifications appropriate for applications in superconducting high performance and quantum computing control systems, which require significant memory resources operating at 4 K.

Design and characterization of superconducting nanowire-based processors for acceleration of deep neural network training.

Training of deep neural networks (DNNs) is a computationally intensive task and requires massive volumes of data transfer. Performing these operations with the conventional von Neumann architectures creates unmanageable time and power costs. Recent studies have shown that mixed-signal designs involving resistive crossbar architectures are capable of achieving acceleration factors as high as 30 000 × over the state of the art digital processors. These approaches involve utilization of non-volatile memory elements as local processors. However, no technology has been developed to-date that can satisfy the strict device requirements for the unit cell. This paper presents the superconducting nanowire-based processing element as a crosspoint device. The unit cell has many programmable non-volatile states that can be used to perform analog multiplication. Importantly, these states are intrinsically discrete due to quantization of flux, which provides symmetric switching characteristics. Operation of these devices in a crossbar is described and verified with electro-thermal circuit simulations. Finally, validation of the concept in an actual DNN training task is shown using an emulator.

Design of a Power Efficient Artificial Neuron Using Superconducting Nanowires.

With the rising societal demand for more information-processing capacity with lower power consumption, alternative architectures inspired by the parallelism and robustness of the human brain have recently emerged as possible solutions. In particular, spiking neural networks (SNNs) offer a bio-realistic approach, relying on pulses, analogous to action potentials, as units of information. While software encoded networks provide flexibility and precision, they are often computationally expensive. As a result, hardware SNNs based on the spiking dynamics of a device or circuit represent an increasingly appealing direction. Here, we propose to use superconducting nanowires as a platform for the development of an artificial neuron. Building on an architecture first proposed for Josephson junctions, we rely on the intrinsic non-linearity of two coupled nanowires to generate spiking behavior, and use electrothermal circuit simulations to demonstrate that the nanowire neuron reproduces multiple characteristics of biological neurons. Furthermore, by harnessing the non-linearity of the superconducting nanowire's inductance, we develop a design for a variable inductive synapse capable of both excitatory and inhibitory control. We demonstrate that this synapse design supports direct fan-out, a feature that has been difficult to achieve in other superconducting architectures, and that the nanowire neuron's nominal energy performance is competitive with that of current technologies.

Construction and characterization of metal ion-containing DNA nanowires for synthetic biology and nanotechnology.

DNA is an attractive candidate for integration into nanoelectronics as a biological nanowire due to its linear geometry, definable base sequence, easy, inexpensive and non-toxic replication and self-assembling properties. Recently we discovered that by intercalating Ag+ in polycytosine-mismatch oligonucleotides, the resulting C-Ag+-C duplexes are able to conduct charge efficiently. To map the functionality and biostability of this system, we built and characterized internally-functionalized DNA nanowires through non-canonical, Ag+-mediated base pairing in duplexes containing cytosine-cytosine mismatches. We assessed the thermal and chemical stability of ion-coordinated duplexes in aqueous solutions and conclude that the C-Ag+-C bond forms DNA duplexes with replicable geometry, predictable thermodynamics, and tunable length. We demonstrated continuous ion chain formation in oligonucleotides of 11-50 nucleotides (nt), and enzyme ligation of mixed strands up to six times that length. This construction is feasible without detectable silver nanocluster contaminants. Functional gene parts for the synthesis of DNA- and RNA-based, C-Ag+-C duplexes in a cell-free system have been constructed in an Escherichia coli expression plasmid and added to the open-source BioBrick Registry, paving the way to realizing the promise of inexpensive industrial production. With appropriate design constraints, this conductive variant of DNA demonstrates promise for use in synthetic biological constructs as a dynamic nucleic acid component and contributes molecular electronic functionality to DNA that is not already found in nature. We propose a viable route to fabricating stable DNA nanowires in cell-free and synthetic biological systems for the production of self-assembling nanoelectronic architectures.

A kinetic-inductance-based superconducting memory element with shunting and sub-nanosecond write times.

We present a kinetic-inductance-based superconducting memory element with non-destructive readout, femtojoule read and write energies, both read and write shunts, which is writeable with pulses shorter than 400 ps. The element utilizes both a high-kinetic-inductance layer made from tungsten silicide as well as a low-kinetic-inductance layer made from niobium. By using tungsten silicide-which has a long (20 ns) thermal time constant-and measuring bit error rates from 10 MHz to 1 GHz, we were able to verify that the thin-film elements could be operated at a data rate at least as fast as the material thermal time constant with a bit error ratio less than 10-6. We also analyze the margins of the device, and outline the characteristics by which a more efficient device may be designed.