Efficient Hybrid Training Method for Neuromorphic Hardware Using Analog Nonvolatile Memory.

Neuromorphic hardware using nonvolatile analog synaptic devices provides promising advantages of reducing energy and time consumption for performing large-scale vector-matrix multiplication (VMM) operations. However, the reported training methods for neuromorphic hardware have appreciably shown reduced accuracy due to the nonideal nature of analog devices, and use conductance tuning protocols that require substantial cost for training. Here, we propose a novel hybrid training method that efficiently trains the neuromorphic hardware using nonvolatile analog memory cells, and experimentally demonstrate the high performance of the method using the fabricated hardware. Our training method does not rely on the conductance tuning protocol to reflect weight updates to analog synaptic devices, which significantly reduces online training costs. When the proposed method is applied, the accuracy of the hardware-based neural network approaches to that of the software-based neural network after only one-epoch training, even if the fabricated synaptic array is trained for only the first synaptic layer. Also, the proposed hybrid training method can be efficiently applied to low-power neuromorphic hardware, including various types of synaptic devices whose weight update characteristics are extremely nonlinear. This successful demonstration of the proposed method in the fabricated hardware shows that neuromorphic hardware using nonvolatile analog memory cells becomes a more promising platform for future artificial intelligence.

Reconfigurable neuromorphic computing block through integration of flash synapse arrays and super-steep neurons.

Neuromorphic computing (NC) architecture inspired by biological nervous systems has been actively studied to overcome the limitations of conventional von Neumann architectures. In this work, we propose a reconfigurable NC block using a flash-type synapse array, emerging positive feedback (PF) neuron devices, and CMOS peripheral circuits, and integrate them on the same substrate to experimentally demonstrate the operations of the proposed NC block. Conductance modulation in the flash memory enables the NC block to be easily calibrated for output signals. In addition, the proposed NC block uses a reduced number of devices for analog-to-digital conversions due to the super-steep switching characteristics of the PF neuron device, substantially reducing the area overhead of NC block. Our NC block shows high energy efficiency (37.9 TOPS/W) with high accuracy for CIFAR-10 image classification (91.80%), outperforming prior works. This work shows the high engineering potential of integrating synapses and neurons in terms of system efficiency and high performance.

Emerging memory technologies for neuromorphic computing.

In this paper, we reviewed the recent trends on neuromorphic computing using emerging memory technologies. Two representative learning algorithms used to implement a hardware-based neural network are described as a bio-inspired learning algorithm and software-based learning algorithm, in particular back-propagation. The requirements of the synaptic device to apply each algorithm were analyzed. Then, we reviewed the research trends of synaptic devices to implement an artificial neural network.

A Split-Gate Positive Feedback Device With an Integrate-and-Fire Capability for a High-Density Low-Power Neuron Circuit.

Hardware-based spiking neural networks (SNNs) to mimic biological neurons have been reported. However, conventional neuron circuits in SNNs have a large area and high power consumption. In this work, a split-gate floating-body positive feedback (PF) device with a charge trapping capability is proposed as a new neuron device that imitates the integrate-and-fire function. Because of the PF characteristic, the subthreshold swing (SS) of the device is less than 0.04 mV/dec. The super-steep SS of the device leads to a low energy consumption of ∼0.25 pJ/spike for a neuron circuit (PF neuron) with the PF device, which is ∼100 times smaller than that of a conventional neuron circuit. The charge storage properties of the device mimic the integrate function of biological neurons without a large membrane capacitor, reducing the PF neuron area by about 17 times compared to that of a conventional neuron. We demonstrate the successful operation of a dense multiple PF neuron system with reset and lateral inhibition using a common self-controller in a neuron layer through simulation. With the multiple PF neuron system and the synapse array, on-line unsupervised pattern learning and recognition are successfully performed to demonstrate the feasibility of our PF device in a neural network.

Analysis on RF parameters of nanoscale tunneling field-effect transistor based on InAs/InGaAs/InP heterojunctions.

Tunneling field-effect transistors (TFETs) based on the quantum mechanical band-to-band tunneling (BTBT) have advantages such as low off-current and subthreshold swing (S) below 60 mV/dec at room temperature. For these reasons, TFETs are considered as promising devices for low standby power (LSTP) applications. On the other hand, silicon (Si)-based TFETs have a drawback in low on-state current (lon) drivability. In this work, we suggest a gate-all-around (GAA) TFET based on compound semiconductors to improve device performances. The proposed device materials consist of InAs (source), InGaAs (channel), and InP (drain). According to the composition (x) of Ga in In1-xGa(x)As layer of the channel region, simulated devices have been investigated in terms of both direct-current (DC) and RF parameters including tunneling rate, transconductance (g(m)), gate capacitance (Cg), intrinsic delay time (tau), cut-off frequency (fT) and maximum oscillation frequency (f(max)). In this study, the obtained maximum values of tau, fT, and f(max) for GAA InAs/In0.9Ga0.1As/InP heterojunction TFET were 21.2 fs, 7 THz, and 18 THz, respectively.