Simulation of Figures of Merit for Barristor Based on Graphene/Insulator Junction.

We investigated the tunneling of graphene/insulator/metal heterojunctions by revising the Tsu-Esaki model of Fowler-Nordheim tunneling and direct tunneling current. Notably, the revised equations for both tunneling currents are proportional to V3, which originates from the linear dispersion of graphene. We developed a simulation tool by adopting revised tunneling equations using MATLAB. Thereafter, we optimized the device performance of the field-emission barristor by engineering the barrier height and thickness to improve the delay time, cut-off frequency, and power-delay product.

Fabricating Graphene Oxide/h-BN Metal Insulator Semiconductor Diodes by Nanosecond Laser Irradiation.

To employ graphene's rapid conduction in 2D devices, a heterostructure with a broad bandgap dielectric that is free of traps is required. Within this paradigm, h-BN is a good candidate because of its graphene-like structure and ultrawide bandgap. We show how to make such a heterostructure by irradiating alternating layers of a-C and a-BN film with a nanosecond excimer laser, melting and zone-refining constituent layers in the process. With Raman spectroscopy and ToF-SIMS analyses, we demonstrate this localized zone-refining into phase-pure h-BN and rGO films with distinct Raman vibrational modes and SIMS profile flattening after laser irradiation. Furthermore, in comparing laser-irradiated rGO-Si MS and rGO/h-BN/Si MIS diodes, the MIS diodes exhibit an increased turn-on voltage (4.4 V) and low leakage current. The MIS diode I-V characteristics reveal direct tunneling conduction under low bias and Fowler-Nordheim tunneling in the high-voltage regime, turning the MIS diode ON with improved rectification and current flow. This study sheds light on the nonequilibrium approaches to engineering h-BN and graphene heterostructures for ultrathin field effect transistor device development.

Giant Magnetoresistance in a Chemical Vapor Deposition Graphene Constriction.

Magnetic field-driven insulating states in graphene are associated with samples of very high quality. Here, this state is shown to exist in monolayer graphene grown by chemical vapor deposition (CVD) and wet transferred on Al2O3 without encapsulation with hexagonal boron nitride (h-BN) or other specialized fabrication techniques associated with superior devices. Two-terminal measurements are performed at low temperature using a GaAs-based multiplexer. During high-throughput testing, insulating properties are found in a 10 µm long graphene device which is 10 µm wide at one contact with an ≈440 nm wide constriction at the other. The low magnetic field mobility is ≈6000 cm2 V-1 s-1. An energy gap induced by the magnetic field opens at charge neutrality, leading to diverging resistance and current switching on the order of 104 with DC bias voltage at an approximate electric field strength of ≈0.04 V µm-1 at high magnetic field. DC source-drain bias measurements show behavior associated with tunneling through a potential barrier and a transition between direct tunneling at low bias to Fowler-Nordheim tunneling at high bias from which the tunneling region is estimated to be on the order of ≈100 nm. Transport becomes activated with temperature from which the gap size is estimated to be 2.4 to 2.8 meV at B = 10 T. Results suggest that a local electronically high quality region exists within the constriction, which dominates transport at high B, causing the device to become insulating and act as a tunnel junction. The use of wet transfer fabrication techniques of CVD material without encapsulation with h-BN and the combination with multiplexing illustrates the convenience of these scalable and reasonably simple methods to find high quality devices for fundamental physics research and with functional properties.

Low Optical Writing Energy Multibit Optoelectronic Memory Based on SnS2 /h-BN/Graphene Heterostructure.

With the rapid development of artificial intelligence and neural network computing, the requirement for information storage in computing is gradually increasing. Floating gate memories based on 2D materials has outstanding characteristics such as non-volatility, optical writing, and optical storage, suitable for application in photonic in-memory computing chips. Notably, the optoelectronic memory requires less optical writing energy, which means lower power consumption and greater storage levels. Here, the authors report an optoelectronic memory based on SnS2 /h-BN/graphene heterostructure with an extremely low photo-generated hole tunneling barrier of 0.23 eV. This non-volatile multibit floating gate memory shows a high switching ratio of 106 and a large memory window range of 64.8 V in the gate range ±40 V. And the memory device can achieve multilevel storage states of 50 under a low power light pulses of 0.32 nW and small light pulse width of 50 ms. Thanks to the Fowler-Nordheim tunneling of the photo-generated holes, the optical writing energy of the optoelectronic memory has been successfully reduced by one to three orders of magnitude compared to existing 2D materials-based systems.

Field Emission Air-Channel Devices as a Voltage Adder.

Field emission air-channel (FEAC) devices can work under atmospheric pressure with a low operation voltage when the electron channel is far less than the mean free path (MFP) in the air, thereby making them a practical component in circuits. Forward and reverse electron emissions of the current FEAC devices demonstrated symmetric Fowler-Nordheim (F-N) plots owing to the symmetric cathode and anode electrodes. This research aimed to demonstrate the arithmetic application of the FEAC devices, their substrate effect, and reliability. A voltage adder was composed of two FEAC devices whose two inputs were connected to two separate function generators, and one output was wire-connected to an oscilloscope. The devices were on a thin dielectric film and low-resistivity silicon substrate to evaluate the parasitic components and substrate effect, resulting in frequency-dependent impedance. The results show that the FEAC devices possessed arithmetic function, but the output voltage decreased. The FEAC devices were still capable of serving as a voltage adder after the reliability test, but electric current leakage increased. Finite element analysis indicated that the highest electrical fields and electron trajectories occur at the apices where the electrons travel with the shortest route less than the MFP in the air, thereby meeting the FEAC devices' design. The modeling also showed that a sharp apex would generate a high electric field at the tip-gap-tip, enhancing the tunneling current.

3D AND-Type Stacked Array for Neuromorphic Systems.

NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler-Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level.

Strongly bias-dependent tunnel magnetoresistance in manganite spin filter tunnel junctions.

A highly unconventional bias-dependent tunnel magnetoresistance (TMR) response is observed in Sm0.75 Sr0.25 MnO3 -based nanopillar spin filter tunnel junctions (SFTJs) with two different behaviors in two different thickness regimes of the barrier layer. Thinner barrier devices exhibit conventional SFTJ behaviors; however, for larger barrier thicknesses, the TMR-bias dependence is more complex and reverses sign at higher bias.

Silicon nanowire charge-trap memory incorporating self-assembled iron oxide quantum dots.

Charge-trap non-volatile memory devices based upon the precise integration of quantum dot storage elements with silicon nanowire field-effect transistors are described. Template-assisted assembly yields an ordered array of FeO QDs within the trenches that separate highly aligned SiNWs, and injected charges are reversibly stored via Fowler-Nordheim tunneling into the QDs. Stored charges shift the transistor threshold voltages, providing the basis for a memory device. Quantum dot size is found to strongly influence memory performance metrics.