Optimisation Challenge for a Superconducting Adiabatic Neural Network That Implements XOR and OR Boolean Functions.

In this article, we consider designs of simple analog artificial neural networks based on adiabatic Josephson cells with a sigmoid activation function. A new approach based on the gradient descent method is developed to adjust the circuit parameters, allowing efficient signal transmission between the network layers. The proposed solution is demonstrated on the example of a system that implements XOR and OR logical operations.

An unsupervised real-time spike sorting system based on optimized OSort.

Objective. The OSort algorithm, a pivotal unsupervised spike sorting method, has been implemented in dedicated hardware devices for real-time spike sorting. However, due to the inherent complexity of neural recording environments, OSort still grapples with numerous transient cluster occurrences during the practical sorting process. This leads to substantial memory usage, heavy computational load, and complex hardware architectures, especially in noisy recordings and multi-channel systems.Approach. This study introduces an optimized OSort algorithm (opt-OSort) which utilizes correlation coefficient (CC), instead of Euclidean distance as classification criterion. TheCCmethod not only bolsters the robustness of spike classification amidst the diverse and ever-changing conditions of physiological and recording noise environments, but also can finish the entire sorting procedure within a fixed number of cluster slots, thus preventing a large number of transient clusters. Moreover, the opt-OSort incorporates two configurable validation loops to efficiently reject cluster outliers and track recording variations caused by electrode drifting in real-time.Main results. The opt-OSort significantly reduces transient cluster occurrences by two orders of magnitude and decreases memory usage by 2.5-80 times in the number of pre-allocated transient clusters compared with other hardware implementations of OSort. The opt-OSort maintains an accuracy comparable to offline OSort and other commonly-used algorithms, with a sorting time of 0.68µs as measured by the hardware-implemented system in both simulated datasets and experimental data. The opt-OSort's ability to handle variations in neural activity caused by electrode drifting is also demonstrated.Significance. These results present a rapid, precise, and robust spike sorting solution suitable for integration into low-power, portable, closed-loop neural control systems and brain-computer interfaces.

ReplaceNet: real-time replacement of a biological neural circuit with a hardware-assisted spiking neural network.

Recent developments in artificial neural networks and their learning algorithms have enabled new research directions in computer vision, language modeling, and neuroscience. Among various neural network algorithms, spiking neural networks (SNNs) are well-suited for understanding the behavior of biological neural circuits. In this work, we propose to guide the training of a sparse SNN in order to replace a sub-region of a cultured hippocampal network with limited hardware resources. To verify our approach with a realistic experimental setup, we record spikes of cultured hippocampal neurons with a microelectrode array (in vitro). The main focus of this work is to dynamically cut unimportant synapses during SNN training on the fly so that the model can be realized on resource-constrained hardware, e.g., implantable devices. To do so, we adopt a simple STDP learning rule to easily select important synapses that impact the quality of spike timing learning. By combining the STDP rule with online supervised learning, we can precisely predict the spike pattern of the cultured network in real-time. The reduction in the model complexity, i.e., the reduced number of connections, significantly reduces the required hardware resources, which is crucial in developing an implantable chip for the treatment of neurological disorders. In addition to the new learning algorithm, we prototype a sparse SNN hardware on a small FPGA with pipelined execution and parallel computing to verify the possibility of real-time replacement. As a result, we can replace a sub-region of the biological neural circuit within 22 µs using 2.5 × fewer hardware resources, i.e., by allowing 80% sparsity in the SNN model, compared to the fully-connected SNN model. With energy-efficient algorithms and hardware, this work presents an essential step toward real-time neuroprosthetic computation.

A Self-Organizing Multi-Layer Agent Computing System for Behavioral Clustering Recognition.

Video behavior recognition often needs to focus on object motion processes. In this work, a self-organizing computational system oriented toward behavioral clustering recognition is proposed, which achieves the extraction of motion change patterns through binary encoding and completes motion pattern summarization using a similarity comparison algorithm. Furthermore, in the face of unknown behavioral video data, a self-organizing structure with layer-by-layer accuracy progression is used to achieve motion law summarization using a multi-layer agent design approach. Finally, the real-time feasibility is verified in the prototype system using real scenes to provide a new feasible solution for unsupervised behavior recognition and space-time scenes.

A Low-Power Analog Integrated Implementation of the Support Vector Machine Algorithm with On-Chip Learning Tested on a Bearing Fault Application.

A novel analog integrated implementation of a hardware-friendly support vector machine algorithm that can be a part of a classification system is presented in this work. The utilized architecture is capable of on-chip learning, making the overall circuit completely autonomous at the cost of power and area efficiency. Nonetheless, using subthreshold region techniques and a low power supply voltage (at only 0.6 V), the overall power consumption is 72 µW. The classifier consists of two main components, the learning and the classification blocks, both of which are based on the mathematical equations of the hardware-friendly algorithm. Based on a real-world dataset, the proposed classifier achieves only 1.4% less average accuracy than a software-based implementation of the same model. Both design procedure and all post-layout simulations are conducted in the Cadence IC Suite, in a TSMC 90 nm CMOS process.

Digital Image Decoder for Efficient Hardware Implementation.

Increasing the resolution of digital images and the frame rate of video sequences leads to an increase in the amount of required logical and memory resources necessary for digital image and video decompression. Therefore, the development of new hardware architectures for digital image decoder with a reduced amount of utilized logical and memory resources become a necessity. In this paper, a digital image decoder for efficient hardware implementation, has been presented. Each block of the proposed digital image decoder has been described. Entropy decoder, decoding probability estimator, dequantizer and inverse subband transformer (parts of the digital image decoder) have been developed in such way which allows efficient hardware implementation with reduced amount of utilized logic and memory resources. It has been shown that proposed hardware realization of inverse subband transformer requires 20% lower memory capacity and uses less logic resources compared with the best state-of-the-art realizations. The proposed digital image decoder has been implemented in a low-cost FPGA device and it has been shown that it requires at least 32% less memory resources in comparison to the other state-of-the-art decoders which can process high-definition frame size. The proposed solution also requires effectively lower memory size than state-of-the-art architectures which process frame size or tile size smaller than high-definition size. The presented digital image decoder has maximum operating frequency comparable with the highest maximum operating frequencies among the state-of-the-art solutions.

A high-performance two-dimensional transform architecture of variable block sizes for the VVC standard.

The versatile video coding standard H.266/VVC release has been accompanied with various new contributions to improve the coding efficiency beyond the high-efficiency video coding (HEVC), particularly in the transformation process. The adaptive multiple transform (AMT) is one of the new tools that was introduced in the transform module. It involves five transform types from the discrete cosine transform/discrete sine transform families with larger block sizes. The DCT-II has a fast computing algorithm, while the DST-VII relies on a complex matrix multiplication. This has led to an additional computational complexity. The approximation of the DST-VII can be used for the transform optimization. At the hardware level, this method can provide a gain in power consumption, logic resources use and speed. In this paper, a unifed two-dimensional transform architecture that enables exact and approximate DST-VII computation of sizes 8 × 8 , 8 × 16 , 8 × 32 , 16 × 8 , 16 × 16 , 16 × 32 , 32 × 8 , 32 × 16 and 32 × 32 is proposed. The exact transform computation can be processed using either multipliers or the MCM algorithm, while the approximate transform computation is based on additions and bit-shifting operations. All the designs are implemented under the Arria 10 FPGA device. The synthesis results show that the proposed design implementing the approximate transform matrices is the most efficient method with only 4% of area consumption. It reduces the logic utilization by more than 65% compared to the multipliers-based exact transform design, while about 53% of hardware cost saving is obtained when compared to the MCM-based computation. Furthermore, the approximate-based 2D transform architecture can operate at 78 MHz allowing a real-time coding for 2K and 4K videos at 100 and 25 frames/s, respectively.

A Learning-Rate Modulable and Reliable TiOx Memristor Array for Robust, Fast, and Accurate Neuromorphic Computing.

Realization of memristor-based neuromorphic hardware system is important to achieve energy efficient bigdata processing and artificial intelligence in integrated device system-level. In this sense, uniform and reliable titanium oxide (TiOx ) memristor array devices are fabricated to be utilized as constituent device element in hardware neural network, representing passive matrix array structure enabling vector-matrix multiplication process between multisignal and trained synaptic weight. In particular, in situ convolutional neural network hardware system is designed and implemented using a multiple 25 × 25 TiOx memristor arrays and the memristor device parameters are developed to bring global constant voltage programming scheme for entire cells in crossbar array without any voltage tuning peripheral circuit such as transistor. Moreover, the learning rate modulation during in situ hardware training process is successfully achieved due to superior TiOx memristor performance such as threshold uniformity (≈2.7%), device yield (> 99%), repetitive stability (≈3000 spikes), low asymmetry value of ≈1.43, ambient stability (6 months), and nonlinear pulse response. The learning rate modulable fast-converging in situ training based on direct memristor operation shows five times less training iterations and reduces training energy compared to the conventional hardware in situ training at ≈95.2% of classification accuracy.

Miniaturization for wearable EEG systems: recording hardware and data processing.

As more people desire at-home diagnosis and treatment for their health improvement, healthcare devices have become more wearable, comfortable, and easy to use. In that sense, the miniaturization of electroencephalography (EEG) systems is a major challenge for developing daily-life healthcare devices. Recently, because of the intertwined relationship between EEG recording and processing, co-research of EEG recording hardware and data processing has been emphasized for whole-in-one miniaturized EEG systems. This paper introduces miniaturization techniques in analog-front-end hardware and processing algorithms for such EEG systems. To miniaturize EEG recording hardware, various types of compact electrodes and mm-sized integrated circuits (IC) techniques including artifact rejection are studied to record accurate EEG signals in a much smaller manner. Active electrode and in-ear EEG technologies are also researched to make small-form-factor EEG measurement structures. Furthermore, miniaturization techniques for EEG processing are discussed including channel selection techniques that reduce the number of required electrode channel and hardware implementation of processing algorithms that simplify the EEG processing stage.

Trade-Off Analysis of Hardware Architectures for Channel-Quality Classification Models.

The latest generation of communication networks, such as SDVN (Software-defined vehicular network) and VANETs (Vehicular ad-hoc networks), should evaluate their communication channels to adapt their behavior. The quality of the communication in data networks depends on the behavior of the transmission channel selected to send the information. Transmission channels can be affected by diverse problems ranging from physical phenomena (e.g., weather, cosmic rays) to interference or faults inherent to data spectra. In particular, if the channel has a good transmission quality, we might maximize the bandwidth use. Otherwise, although fault-tolerant schemes degrade the transmission speed by solving errors or failures should be included, these schemes spend more energy and are slower due to requesting lost packets (recovery). In this sense, one of the open problems in communications is how to design and implement an efficient and low-power-consumption mechanism capable of sensing the quality of the channel and automatically making the adjustments to select the channel over which transmit. In this work, we present a trade-off analysis based on hardware implementation to identify if a channel has a low or high quality, implementing four machine learning algorithms: Decision Trees, Multi-Layer Perceptron, Logistic Regression, and Support Vector Machines. We obtained the best trade-off with an accuracy of 95.01% and efficiency of 9.83 Mbps/LUT (LookUp Table) with a hardware implementation of a Decision Tree algorithm with a depth of five.

Adapting a Dehazing System to Haze Conditions by Piece-Wisely Linearizing a Depth Estimator.

Haze is the most frequently encountered weather condition on the road, and it accounts for a considerable number of car crashes occurring every year. Accordingly, image dehazing has garnered strong interest in recent decades. However, although various algorithms have been developed, a robust dehazing method that can operate reliably in different haze conditions is still in great demand. Therefore, this paper presents a method to adapt a dehazing system to various haze conditions. Under this approach, the proposed method discriminates haze conditions based on the haze density estimate. The discrimination result is then leveraged to form a piece-wise linear weight to modify the depth estimator. Consequently, the proposed method can effectively handle arbitrary input images regardless of their haze condition. This paper also presents a corresponding real-time hardware implementation to facilitate the integration into existing embedded systems. Finally, a comparative assessment against benchmark designs demonstrates the efficacy of the proposed dehazing method and its hardware counterpart.

Features of hardware implementation of quasi-continuous observation devices with discrete receivers.

This article proposes an approach to the formalization of tasks and conditions for the hardware implementation of quasi-continuous observation devices with discrete receivers in remote sensing systems. Observation devices with a matrix are used in medicine, ecology, aerospace photography, and geodesy, among other fields. In the discrete receivers, the sampling of an image in the matrix receiver into pixels leads to a decrease in the spatial information of the object. In a greater extent, these disadvantages can be avoided by using photosensitive matrix with a regularly changing (controlled) density of elementary receivers-matrix (RCDOER-matrix). Currently, there is no substantiation of the tasks and conditions for the hardware implementation of RCDOER-matrix. The algorithmic formation of a quasi-continuous image of observation devices with the RCDOER-matrix is proposed. The algorithm used a formal pixel-by-pixel description of the signals in the image. This algorithm formalizes the requirements for creating a photosensitive RCDOER-matrix of a certain size, as well as for changing the mechanism for forming and saving a frame with observation results. The application of the developed method will allow multiplying the pixel size of the image relative to the pixel size of the RCDOER-matrix. Developed algorithms for RCDOER-matrix are supplemented by formalizing the tasks that arise when creating prototypes. In addition, the conditions for hardware implementation are proposed, which ensure the completeness of registration of the observation picture, and allow avoiding excessive pixel measurements. Thus, the results of the research carried out approximate the practical application of RCDOER-matrix.

An efficient design for real-time obstructive sleep apnea OSA detection through esophageal pressure Pes signal.

Obstructive Sleep Apnea (OSA) is a potentially common sleep disorder in which the upper airways are collapsed either partially or completely. The golden standard method for treating OSA, is the full night Continuous Positive Airway Pressure (CPAP). Yet, due to the ensuing discomfort, it incurs on patients, researchers have been motivated to investigate other alternatives, whereby, OSA can be effectively treated. Recently, an increasingly popular OSA treatment has been developed that consists in activating the protrusion muscles of the tongue by stimulating the Hypoglossal Nerve (HGN). In this context, the present work is conducted to propose the design of apnea detector module as part of an implantable HGN stimulator based on the esophageal Pressure Pes signal as a new approach for controlling OSA occurrence. Specifically, an effective real-time apnea event detecting algorithm is put forward. Following the achievement of satisfactory simulation results, attained through the Modelsim simulation tool, we proceeded with assessing the possibility of its hardware implementation on a Field-Programmable Gate Array (FPGA) device. To this end, the apnea detector module was synthesized and designed. The low power consumption and the small size, characterizing this module, which have made it possible to integrate it as part of a wirelessly-powered implantable HGN stimulator.

Design and Implementation of a Real-Time Multi-Beam Sonar System Based on FPGA and DSP.

Aiming at addressing the contradiction between the high-speed real-time positioning and multi-channel signal processing in multi-beam sonar systems, in this work we present a real-time multi-beam sonar system based on a Field Programmable Gate Array (FPGA) and Digital Signal Processing (DSP) from two perspectives, i.e., hardware implementation and software optimization. In terms of hardware, an efficient high-voltage pulse transmitting module and a multi-channel data acquisition module with time versus gain (TVG) compensation with characteristics such as low noise and high phase amplitude consistency, are proposed. In terms of algorithms, we study three beamforming methods, namely delay-and-sum (D&S), direct-method (DM) and Chirp Zeta Transform (CZT). We compare the computational efficiency of DM and CZT in the digital domain. In terms of software, according to the transmission bandwidth of the Gigabit Ethernet and a serial rapid IO (SRIO) interface, the data transmission paths of the acquired data and the beam pattern between the FPGA, the DSP, and a personal computer (PC) are planned. A master-slave multi-core pipelined signal processing architecture is designed based on DSP, which enhances the data throughput of the signal processor by seven times as compared with that of the single-core operation. The experimental results reveal that the sound source level of the transmitting module is around 190.25 dB, the transmitting beam width is 64° × 64°, the background noise of the acquisition module is less than 4 µVrms, the amplitude consistency error of each channel is less than -6.55 dB, and the phase consistency error is less than 0.2°. It is noteworthy that the beam number of the sonar system is 90 × 90, the scanning angle interval is 0.33°, the working distance ranges from 5 m to 40 m, and the maximum distance resolution is 0.384 m. In the positioning experiment performed in this work; the 3-D real-time position of the baffle placed in the detection sector is realized. Please note that the maximum deviation of azimuth is 2°, the maximum deviation of elevation is 2.3°, and the maximum distance deviation is 0.379 m.

A Comparison of Energy-Efficient Seizure Detectors for Implantable Neurostimulation Devices.

Introduction: About 30% of epilepsy patients are resistant to treatment with antiepileptic drugs, and only a minority of these are surgical candidates. A recent therapeutic approach is the application of electrical stimulation in the early phases of a seizure to interrupt its spread across the brain. To accomplish this, energy-efficient seizure detectors are required that are able to detect a seizure in its early stages. Methods: Three patient-specific, energy-efficient seizure detectors are proposed in this study: (i) random forest (RF); (ii) long short-term memory (LSTM) recurrent neural network (RNN); and (iii) convolutional neural network (CNN). Performance evaluation was based on EEG data (n = 40 patients) derived from a selected set of surface EEG electrodes, which mimic the electrode layout of an implantable neurostimulation system. As for the RF input, 16 features in the time- and frequency-domains were selected. Raw EEG data were used for both CNN and RNN. Energy consumption was estimated by a platform-independent model based on the number of arithmetic operations (AOs) and memory accesses (MAs). To validate the estimated energy consumption, the RNN classifier was implemented on an ultra-low-power microcontroller. Results: The RNN seizure detector achieved a slightly better level of performance, with a median area under the precision-recall curve score of 0.49, compared to 0.47 for CNN and 0.46 for RF. In terms of energy consumption, RF was the most efficient algorithm, with a total of 67k AOs and 67k MAs per classification. This was followed by CNN (488k AOs and 963k MAs) and RNN (772k AOs and 978k MAs), whereby MAs contributed more to total energy consumption. Measurements derived from the hardware implementation of the RNN algorithm demonstrated a significant correlation between estimations and actual measurements. Discussion: All three proposed seizure detection algorithms were shown to be suitable for application in implantable devices. The applied methodology for a platform-independent energy estimation was proven to be accurate by way of hardware implementation of the RNN algorithm. These findings show that seizure detection can be achieved using just a few channels with limited spatial distribution. The methodology proposed in this study can therefore be applied when designing new models for responsive neurostimulation.

Real-time epileptic seizure prediction based on online monitoring of pre-ictal features.

Reliable prediction of epileptic seizures is of prime importance as it can drastically change the quality of life for patients. This study aims to propose a real-time low computational approach for the prediction of epileptic seizures and to present an efficient hardware implementation of this approach for portable prediction systems. Three levels of feature extraction are performed to characterize the pre-ictal activities of the EEG signal. In the first-level, the line length algorithm is applied to the pre-ictal region. The features obtained in the first-level are mathematically integrated to extract the second-level features and then the line lengths of the second-level features are calculated to obtain our third-level feature. The third-level information is compared with predefined threshold levels to make a decision on whether the extracted characteristics are relevant to a seizure occurrence or not. The validity of this algorithm was tested by EEG recordings in the CHB-MIT database (97 seizures, 834.224 h) for 19 epileptic patients. The results showed that the average sensitivity was 90.62%, the specificity was 88.34%, the accuracy was 88.76% with the average false prediction rate as low as 0.0046 h-1, and the average prediction time was 23.3 min. The low computational complexity is the superiority of the proposed approach, which provides a technologically simple but accurate way of predicting epileptic seizures and enables hardware implantable devices. Graphical abstract Proposed seizure prediction algorithm and its features.

Non-invasive improved technique for lumbar discus hernia classification based on fuzzy logic.

This paper presents the improved technique for classification of the type of lumbar discus hernia based on fuzzy logic. The reduced mobility of the foot is one of the symptoms of the disease that occurs because of the displaced discs in the space of two vertebrae. This fact was used for non-invasive discus hernia diagnosis by measuring force values from four sensors placed on both feet (first, second and fourth metatarsal head as well as the heel). Hardware and software systems were constructed for the doctor to perform the measurements and have a graphical representation during the measuring procedure. The procedure included measuring force values of 18 subjects during normal standing, standing on forefeet and heels. All subjects were diagnosed by a specialist with either L4/L5 or L5/S1 discus hernia. Filtering and further preprocessing of acquired values included separation of forefeet and heel segments that were used as inputs to fuzzy system. The results showed that the accuracy of such a fuzzy system was around 72%, and the proposed system correctly recognizes healthy individuals. Obtained information about forces on characteristic points on the foot represents useful data in diagnosis which further can be processed in order to be a supportive tool to doctors.

Adaptive Real-Time Removal of Impulse Noise in Medical Images.

Noise is an important factor that degrades the quality of medical images. Impulse noise is a common noise caused by malfunctioning of sensor elements or errors in the transmission of images. In medical images due to presence of white foreground and black background, many pixels have intensities similar to impulse noise and hence the distinction between noisy and regular pixels is difficult. Therefore, it is important to design a method to accurately remove this type of noise. In addition to the accuracy, the complexity of the method is very important in terms of hardware implementation. In this paper a low complexity de-noising method is proposed that distinguishes between noisy and non-noisy pixels and removes the noise by local analysis of the image blocks. All steps are designed to have low hardware complexity. Simulation results show that in the case of magnetic resonance images, the proposed method removes impulse noise with an acceptable accuracy.

A Digital Hardware Realization for Spiking Model of Cutaneous Mechanoreceptor.

Inspired by the biology of human tactile perception, a hardware neuromorphic approach is proposed for spiking model of mechanoreceptors to encode the input force. In this way, a digital circuit is designed for a slowly adapting type I (SA-I) and fast adapting type I (FA-I) mechanoreceptors to be implemented on a low-cost digital hardware, such as field-programmable gate array (FPGA). This system computationally replicates the neural firing responses of both afferents. Then, comparative simulations are shown. The spiking models of mechanoreceptors are first simulated in MATLAB and next the digital neuromorphic circuits simulated in VIVADO are also compared to show that obtained results are in good agreement both quantitatively and qualitatively. Finally, we test the performance of the proposed digital mechanoreceptors in hardware using a prepared experimental set up. Hardware synthesis and physical realization on FPGA indicate that the digital mechanoreceptors are able to replicate essential characteristics of different firing patterns including bursting and spiking responses of the SA-I and FA-I mechanoreceptors. In addition to parallel computation, a main advantage of this method is that the mechanoreceptor digital circuits can be implemented in real-time through low-power neuromorphic hardware. This novel engineering framework is generally suitable for use in robotic and hand-prosthetic applications, so progressing the state of the art for tactile sensing.