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An Ultra-Low-Power Analog Multiplier-Divider Compatible with Digital Code for RRAM-Based Computing-in-Memory Macros.
Yang, Yiming; Lv, Shidong; Li, Xiaoran; Wang, Xinghua; Wang, Qian; Yuan, Yiyang; Liang, Sen; Zhang, Feng.
Afiliação
  • Yang Y; School of Integrated Circuits and Electronics, Beijing Institute of Technology, Beijing 100081, China.
  • Lv S; School of Integrated Circuits and Electronics, Beijing Institute of Technology, Beijing 100081, China.
  • Li X; School of Integrated Circuits and Electronics, Beijing Institute of Technology, Beijing 100081, China.
  • Wang X; BIT Chongqing Institute of Microelectronics and Microsystems, Chongqing 401332, China.
  • Wang Q; School of Integrated Circuits and Electronics, Beijing Institute of Technology, Beijing 100081, China.
  • Yuan Y; BIT Chongqing Institute of Microelectronics and Microsystems, Chongqing 401332, China.
  • Liang S; Yangtze Delta Region Academy of Beijing Institute of Technology, Jiaxing 314000, China.
  • Zhang F; School of Integrated Circuits and Electronics, Beijing Institute of Technology, Beijing 100081, China.
Micromachines (Basel) ; 14(7)2023 Jul 24.
Article em En | MEDLINE | ID: mdl-37512793
ABSTRACT
This manuscript presents an ultra-low-power analog multiplier-divider compatible with digital code words, which is applicable to the integrated structure of resistive random-access memory (RRAM)-based computing-in-memory (CIM) macros. Current multiplication and division are accomplished by a current-mirror-based structure. Compared with digital dividers to achieve higher precision and operation speed, analog dividers present the advantages of a reduced power consumption and a simple circuit structure in lower precision operations, thus improving the energy efficiency. Designed and fabricated in a 55 nm CMOS process, the proposed work is capable of achieving 8-bit precision for analog current multiplication and division operations. Measurement results show that the signal delay is 1 µs when performing 8-bit operation, with a bandwidth of 1.4 MHz. The power consumption is less than 6.15 µW with a 1.2 V supply voltage. The proposed multiplier-divider can increase the operation capacity by dividing the input current and digital code while reducing the power consumption and complexity required by division, which can be further utilized in real-time operation of edge computing devices.
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Texto completo: 1 Base de dados: MEDLINE Idioma: En Ano de publicação: 2023 Tipo de documento: Article

Texto completo: 1 Base de dados: MEDLINE Idioma: En Ano de publicação: 2023 Tipo de documento: Article