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A Novel DTSCR Structure with High Holding Voltage and Enhanced Current Discharge Capability for 28 nm CMOS Technology ESD Protection.
Han, Zeen; Chen, Shupeng; Liu, Hongxia; Wang, Shulong; Ma, Boyang; Chen, Ruibo; Fu, Xiaojun.
Afiliação
  • Han Z; Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices of Education, The School of Microelectronics, Xidian University, Xi'an 710071, China.
  • Chen S; Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices of Education, The School of Microelectronics, Xidian University, Xi'an 710071, China.
  • Liu H; Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices of Education, The School of Microelectronics, Xidian University, Xi'an 710071, China.
  • Wang S; Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices of Education, The School of Microelectronics, Xidian University, Xi'an 710071, China.
  • Ma B; Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices of Education, The School of Microelectronics, Xidian University, Xi'an 710071, China.
  • Chen R; Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices of Education, The School of Microelectronics, Xidian University, Xi'an 710071, China.
  • Fu X; National Key Laboratory of Integrated Circuits and Microsystems, Chongqing 401332, China.
Micromachines (Basel) ; 15(1)2023 Dec 31.
Article em En | MEDLINE | ID: mdl-38258215
ABSTRACT
To cope with the much narrower ESD design window in 28 nm CMOS technology, a novel diode-triggered silicon-controlled rectifier with an extra discharge path (EDP-DTSCR) for ESD protection is proposed in this paper. Compared with the traditional DTSCR, the proposed DTSCR has an enhanced current discharge capability that is achieved by creating a slave SCR path in parallel with the master SCR path. Moreover, the improved triggering and holding characteristic can be obtained by the proposed EDP-DTSCR. By sharing the anode emitter junction, a slave SCR path is constructed that is symmetrical to the position of the master SCR path to add an additional ESD discharge path to the EDP-DTSCR. In this way, the current discharge capability of the entire device is obviously improved. The TCAD simulation result shows that the proposed device has a remarkably lower on-resistance compared with the traditional DTSCR and the DTSCR with p-type guard ring (PGR-DTSCR). In addition, it is structurally optimized to further increase the holding voltage and reduce the trigger voltage to improve the anti-latching capability of the device, which is more conducive to the ESD protection window application of 28 nm CMOS technology.
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Texto completo: 1 Base de dados: MEDLINE Idioma: En Ano de publicação: 2023 Tipo de documento: Article

Texto completo: 1 Base de dados: MEDLINE Idioma: En Ano de publicação: 2023 Tipo de documento: Article