Scaling Effect on Silicon Nitride Memristor with Highly Doped Si Substrate.

A feasible approach is reported to reduce the switching current and increase the nonlinearity in a complementary metal-oxide-semiconductor (CMOS)-compatible Ti/SiNx /p+ -Si memristor by simply reducing the cell size down to sub-100 nm. Even though the switching voltages gradually increase with decreasing device size, the reset current is reduced because of the reduced current overshoot effect. The scaled devices (sub-100 nm) exhibit gradual reset switching driven by the electric field, whereas that of the large devices (≥1 µm) is driven by Joule heating. For the scaled cell (60 nm), the current levels are tunable by adjusting the reset stop voltage for multilevel cells. It is revealed that the nonlinearity in the low-resistance state is attributed to Fowler-Nordheim tunneling dominating in the high-voltage regime (≥1 V) for the scaled cells. The experimental findings demonstrate that the scaled metal-nitride-silicon memristor device paves the way to realize CMOS-compatible high-density crosspoint array applications.

Interface-modified unipolar resistive random access memory (RRAM) structure for low-power application.

An interface-engineered resistive random access memory (RRAM) using bilayer transition metal oxide (TMO) is presented for improving unipolar resistive-switching characteristics. The experiment and simulation data show that better resistive switching characteristics and superb uniformity can be realized by inserting a thin AIOx insertion layer between the Ir/NiO interface. To elucidate the uniformity improvement of our bilayer structure, the conducting-defect effects in the resistive cell were also investigated using a random circuit breaker (RCB) simulation model. It has been verified that the forming and set characteristics are more effectively improved because the conducting-defect ratio in the insertion layer region is low, therefore making it more advantageous for a filament path controllability. Using the optimal oxygen contents in both the insertion layer and the resistive cell, it was confirmed that a significant reduction of up to 0.15 mA of the reset current (I(RESET)) is possible compared to the conventional cell. These results indicate that new AI insertion has a large contribution to the reset and forming processes.

Dimensional effect of non-polar resistive random access memory (RRAM) for low-power memory application.

The relationships between the resistive cell dimension and the related analytical parameters such as the forming voltage, set voltage, and reset current were investigated to implement high-density and low-power unipolar RRAM. It was shown that the formation process in unipolar switching is strongly related to the cell dimension in the sub-nm region, not only in terms of its vertical thickness but also of its horizontal length, using the numerical simulation method. With the optimal cell size having sufficient initial resistance and a low forming voltage, the achievement of the greatest feasibility of the high-density low-power RRAM will be further accelerated. A numerical simulation was performed using a random circuit breaker (RCB) simulation model to investigate the optimal resistive switching condition. The on/off resistance ratio increases as the cell area decreases at the sub-nm level, and these phenomena are explained in terms of the relatively large set resistance change in a very small area due to the conductive defect (CD) amount effect in the RCB network model.

Split-gate-structure 1T DRAM for retention characteristic improvement.

As the feature size of the conventional 1T-1C DRAM scales down, difficulties of the fabrication process are increasing and it is becoming harder to keep a constant capacitance value for data storage. Capacitor-less 1T DRAM is a promising candidate for the substitution of the conventional 1T-1C DRAM, but its poor retention time is one of the critical issues in its commercialization. In the selection of a bias condition for 1T DRAM, however, it is impossible to choose a gate bias condition that is suitable for both the "1" and "0" hold state data. In this paper, a split gate structure and hold bias scheme are proposed for the simultaneous improvement of the "1" and "0" data retention characteristics. It was confirmed through numerical simulation that this structure has a more than 3 sec retention time. A vertical gate-all-around split-gate structure and its fabrication method are also suggested to achieve high density, low cost, a higher sensing margin, and a longer retention time.