The immunoglobulin superfamily member CD200R identifies cells involved in type 2 immune responses.

BACKGROUND: The pathology of allergic diseases involves type 2 immune cells, such as Th2, ILC2, and basophils exerting their effect by production of IL-4, IL-5, and IL-13. However, surface receptors that are specifically expressed on type 2 immune cells are less well documented. The aim of this investigation was to identify surface markers associated with type 2 inflammation. METHODS: Naïve human CD4+ T cells were short-term activated in the presence or absence of IL-4 and analyzed for expression of >300 cell-surface proteins. Ex vivo-isolated peripheral blood mononuclear cells (PBMCs) from peanut-allergic (PA) and nonallergic subjects were stimulated (14-16 h) with peanut extract to detect peanut-specific CD4+ CD154+ T cells. Biopsies were obtained for transcriptomic analysis from healthy controls and patients with extrinsic or intrinsic atopic dermatitis (AD) and psoriasis. RESULTS: Expression analysis of >300 surface proteins enabled identification of IL-4-upregulated surface proteins, such as CD90, CD108, CD109, and CD200R (CD200R1). Additional analysis of in vitro-differentiated Th0, Th1, and Th2 cultures identified CD200R as upregulated on Th2 cells. From ex vivo-isolated PBMCs, we found high expression of CD200R on Th2 and ILC2 cells and basophils. In PA subjects, the peanut-specific Th2 (CD154+ CRTh2+ ) cells expressed more CD200R than the non-allergen-specific Th2 (CD154- CRTh2+ ) cells. Moreover, costaining of CD161 and CD200R identified peanut-specific highly differentiated IL-4+ IL-5+ Th2 cells. Finally, transcriptomic analysis revealed upregulation of CD200R in lesional skin from subjects with an extrinsic AD phenotype compared to healthy skin. CONCLUSION: These results indicate that CD200R expression strongly correlates with Th2 pathology; though, the mechanism is as yet elusive.

Performance scaling comparison for free-space optical and electrical interconnection approaches.

Projected performance metrics of free-space optical and electrical interconnections are estimated and compared in terms of smart-pixel input-output bandwidth density and practical geometric packaging constraints. The results suggest that three-dimensional optical interconnects based on smart pixels provide the highest volume, latency, and power-consumption benefits for applications in which globally interconnected networks are required to implement links across many integrated-circuit chips. It is further shown that interconnection approaches based on macro-optical elements achieve better scaling than those based on micro-optical elements. The scaling limits of micro-optical-based architectures stem from the need for repeaters to overcome diffraction losses in multichip architectures with high bisection bandwidth. The overall results provide guidance in determining whether and how strongly a free-space optical interconnection approach can be applied to a given multiprocessor problem.

Two-bounce optical arbitrary permutation network.

The two-bounce free-space arbitrary interconnection architecture is presented. It results from a series of three-dimensional topological transformations to the Benes network, the minimum rearrangeable nonblocking network. Although functionally equivalent to the Benes network, it requires only two stages of global (spanning multiple chips) optical interconnections. The remaining stages of the modified Benes interconnection network are local and are implemented electronically (on individual chips). The two-bounce network is optimal in the sense that it retains the Benes minimum number of electronic switching resources yet also minimizes the number of optical links needed for global interconnection. Despite the use of higher-order k-shuffle (k > 2) global optical interconnects, the number of 2 x 2 switching elements is identical to the two-shuffle Benes network: there is no need for k x k crossbar switches for local interconnection at each stage. An experimental validation of the two-bounce architecture is presented.

Sliding-banyan network performance analysis.

The sliding-banyan (SB) network employs an interleaved multistage shuffle-exchange topology, implemented with a three-dimensional free-space interconnection architecture that connects a multichip backplane to itself. Surface-normal emitters and detectors, which compose the stages' input-output, are spatially multiplexed within the same chip location, along with electronic control and switching resources. A simple deflection self-routing scheme minimizes internal contention, providing efficient use of switching and interconnection resources. The blocking performance of the SB is quantified through simulations based on realistic nonuniform traffic patterns. Results show that the SB architecture requires significantly fewer resources than other self-routing banyan-based networks. The multistage-switching and interconnection-resource requirements are close to the theoretical minimum for nonblocking networks, and the SB's distributed self-routing control resources grow only approximately linearly with the number of nodes, providing good scalability.

Low-distortion hybrid optical shuffle concept.

A hybrid micro-macro-optical shuffle interconnection approach is described. The new concept minimizes distortion in multichip smart-pixel shuffle interconnection systems that use macro-optics to link dense arrays of vertical-cavity surface-emitting laser (VCSEL) sources and matching arrays of detectors. The typical narrow-beam cones of VCSEL's are exploited by use of beam-deflecting micro-optics to create an optical system that is symmetric about its aperture. Since symmetric systems are well known to cancel distortion, this novel concept provides the means to achieve the required high degree of interchip registration accuracy.

Multichip free-space global optical interconnection demonstration with integrated arrays of vertical-cavity surface-emitting lasers and photodetectors.

The experimental optical interconnection module of the Free-Space Accelerator for Switching Terabit Networks (FAST-Net) project is described and characterized. Four two-dimensional (2-D) arrays of monolithically integrated vertical-cavity surface-emitting lasers (VCSEL's) and photodetectors (PD's) were designed, fabricated, and incorporated into a folded optical system that links a 10 cm x 10 cm multichip smart pixel plane to itself in a global point-to-point pattern. The optical system effects a fully connected network in which each chip is connected to all others with a multichannel bidirectional data path. VCSEL's and detectors are arranged in clusters on the chips with an interelement spacing of 140 microm. Calculations based on measurements of resolution and registration tolerances showed that the square 50-microm detector in a typical interchip link captures approximately 85% of incident light from its associated VCSEL. The measured optical transmission efficiency was 38%, with the losses primarily due to reflections at the surfaces of the multielement lenses, which were not antireflection coated for the VCSEL wavelength. The overall efficiency for this demonstration is therefore 32%. With the measured optical confinement, an optical system that is optimized for transmission at the VCSEL wavelength will achieve an overall efficiency of greater than 80%. These results suggest that, as high-density VCSEL-based smart pixel technology matures, the FAST-Net optical interconnection concept will provide a low-loss, compact, global interconnection approach for high bisection-bandwidth multiprocessor applications in switching, signal processing, and image processing.