RESUMEN
In this study, a two-dimensional electron gas (2DEG), which is a conductive layer formed at the interface of Al2O3and TiO2, was used as an electrode for resistive random access memory (RRAM) and implemented in a cell size down to 30 nm. For an RRAM device comprising W/2DEG/TiO2/W, we confirmed that the dominant switching mechanism changed from interfacial to filamentary as the cell size decreased from 500 nm to 30 nm. Through analyses of changes in forming characteristics and conduction mechanisms in the low resistive state depending on the cell size, it was identified that the 2DEG acted as an oxygen-scavenging layer of TiO2during the resistive switching process. By comparing the switching characteristics of RRAM devices with and without 2DEG for a 30 nm cell size, we confirmed that a high-performance 2DEG RRAM was realized, with highly uniform current-voltage characteristics, a low operating voltage (â¼1 V), and a high on/off ratio (>102). Finally, the applicability of the proposed device to a crossbar array was validated by evaluating 1S1R operation with an NbO2-based selector. Considering the improved switching uniformity, the 2DEG RRAM shows promise for high-density memory applications.
RESUMEN
Synapse devices are essential for the hardware implementation of neuromorphic computing systems. However, it is difficult to realize ideal synapse devices because of issues such as nonlinear conductance change (linearity) and a small number of conductance states (dynamic range). In this study, the correlation between the linearity and dynamic range was investigated. Consequently, we found a trade-off relationship between the linearity and dynamic range and proposed a novel training method to overcome this trade-off.
RESUMEN
A synaptic device with a multilayer structure is proposed to reduce the operating power of neuromorphic computing systems while maintaining a high-density integration. A simple metal-insulator-metal (MIM)-structured multilayer synaptic device is developed using an 8-inch wafer-based and complementary metal-oxide-semiconductor (CMOS) fabrication process. The three types of MIM-structured synaptic devices are compared to assess their effects on reducing the operating power. The obtained results exhibited low-power operation owing to the inserted layers acting as an internal resistor. The modulated operational conductance level and simple MIM structure demonstrate the feasibility of implementing both low-power operation and high-density integration in multilayer synaptic devices.
RESUMEN
For portable and transparent electronic applications, transparent supercapacitor (T-SC) is developed to act as an energy storing device. Because electric and optical characteristics of the supercapacitor are strongly dependent on its thickness, all solid state T-SC was developed based on sensitively controllable fabrication process. We were able to attain an optimum thickness for the T-SC such that it exhibited an excellent transparency as well as capacity. Thus, the transparency-capacity dilemma, that is, the thickness of a T-SC increases with respect to its capacity while it is inversely proportional to its transparency, was solved through our proposed T-SC structure. Consequently, more than 60% transparency and 80% capacitance retention of 1500 charge/discharge cycles were achieved. The overcoming of transparency-capacity dilemma can enhance the T-SC applicability as a core energy storage device.
RESUMEN
A metal-insulator-metal-structured Ag-filament-based transparent threshold switch is developed as a selector device for a crossbar array, which can lead to high-density integration of advanced memory devices. Both threshold switching and rectifying behavior were achieved based on sensitive control of the filament size. Conduction mechanism analyses demonstrated that the rectifying behavior resulted from the Schottky barrier at the interface. From the threshold switching, including the rectifying behavior, the available crossbar array size is 105-times larger.
RESUMEN
Lately, there has been a rapid increase in the use of software-based deep learning neural networks (S-DNN) for the analysis of unstructured data consumption. For implementation of the S-DNN, synapse-device-based hardware DNN (H-DNN) has been proposed as an alternative to typical Von-Neumann structural computing systems. In the H-DNN, various numerical values such as the synaptic weight, activation function, and etc., have to be realized through electrical device or circuit. Among them, the synaptic weight that should have both positive and negative numerical values needs to be implemented in a simpler way. Because the synaptic weight has been expressed by conductance value of the synapse device, it always has a positive value. Therefore, typically, a pair of synapse devices is required to realize the negative weight values, which leads to additional hardware resources such as more devices, higher power consumption, larger area, and increased circuit complexity. Herein, we propose an alternative simpler method to realize the negative weight (named weight shifter) and its hardware implementation. To demonstrate the weight shifter, we investigated its theoretical, numerical, and circuit-related aspects, following which the H-DNN circuit was successfully implemented on a printed circuit board.