Simulation Program with Integrated Circuit Emphasis Compact Modeling of a Dual-Gate Positive-Feedback Field-Effect Transistor for Circuit Simulations.

In this work, we developed a SPICE compact model of a dual-gate positive-feedback field-effect transistor (FBFET) for circuit simulations by fitting the model to measurement results. We fabricated a FBFET and investigated the DC and transient characteristics. The fabricated FBFET has an extremely low sub-threshold slope and a low off current. The FBFET operates as a forward-biased PN diode after the device is turned on due to the positive feedback loop between the integrated charges and the potential barrier. When enough electrons are accumulated in the floating body, the potential barrier is lowered and the FBFET is turned on rapidly, and due to the integrated charges, the FBFET has memory characteristics which approximate hose of 1T-DRAM. Reflecting these electrical characteristics of the FBFET, we undertook SPICE modeling and obtained simulation results that were similar to the measurement characteristics. Finally, we implement a modified inverter with the FBFET connected in parallel with an n-type MOSFET (NMOS). Due to the superior sub-threshold characteristics of the FBFET, it effectively suppresses the sub-threshold currents.

Analysis of Hot Carrier Injection According to Gate Length.

In this paper, we analyze hot carrier injection (HCI) in an asymmetric dual gate structure with a charge storage layer. In a floating gate device, holes injected by HCI can move freely in the valence band, since the channel potential is constant. In case of charge trapping layer, however, holes are trapped only in the drain side where impact ionization occurs. Therefore, only small threshold voltage shift occurs because channel formation is enhanced only in the drain side. When the gate length is under 100 nm, trapped holes in the drain side start to control the whole channel. Thus, we expect that HCI into the charge trapping layer can be used as a non-volatile memory (NVM) mechanism in short channel devices.

Analysis of Minority Carrier Lifetime Dependence on Dual Gate Feedback Field Effect Transistor.

In this paper, we investigated the dependence of minority carrier lifetime on dual gate FBFET. Generally, depending on the channel condition or trap density, the lifetime of minority carrier can be degraded. Since the potential barrier lowering through the accumulated carriers is essential for positive feedback, the deterioration of lifetime can make a critical influence on the operation of device. Therefore, we verified the tendency of threshold voltage according to carrier lifetime and channel length. Through the comparison with p-n diode and FBFET, we drew the relation between lifetime and threshold voltage. As a result, it has been confirmed that the device with significantly deteriorated lifetime or the device with extremely long channel does not effectively generate feedback and loses its steep switching characteristics.

Realization of Multiple Synapse Plasticity by Coexistence of Volatile and Nonvolatile Characteristics of Interface Type Memristor.

Studies on neuromorphic computing systems are becoming increasingly important in the big-data-processing era as these systems are capable of energy-efficient parallel data processing and can overcome the present limitations owing to the von Neumann bottleneck. The Pt/WOx/ITO resistive random-access memory device can be used to implement versatile synapse functions because it possesses both volatile and nonvolatile characteristics. The gradual increase and decrease in the current of the Pt/WOx/ITO device with its uniform resistance state for endurance and retention enables additional synaptic applications that can be controlled using electric pulses. If the volatile and nonvolatile device properties are set through rehearsal and forgetting processes, the device can emulate various synaptic behaviors, such as potentiation and depression, paired-pulse facilitation, post-tetanic potentiation, image training, Hebbian learning rules, excitatory postsynaptic current, and Pavlov's test. Furthermore, reservoir computing can be implemented for applications such as pattern generation and recognition. This emphasizes the various applications of future neuromorphic devices, demonstrating the various favorable characteristics of pulse-enhanced Pt/WOx/ITO devices.

Low-Latency Spiking Neural Networks Using Pre-Charged Membrane Potential and Delayed Evaluation.

Spiking neural networks (SNNs) have attracted many researchers' interests due to its biological plausibility and event-driven characteristic. In particular, recently, many studies on high-performance SNNs comparable to the conventional analog-valued neural networks (ANNs) have been reported by converting weights trained from ANNs into SNNs. However, unlike ANNs, SNNs have an inherent latency that is required to reach the best performance because of differences in operations of neuron. In SNNs, not only spatial integration but also temporal integration exists, and the information is encoded by spike trains rather than values in ANNs. Therefore, it takes time to achieve a steady-state of the performance in SNNs. The latency is worse in deep networks and required to be reduced for the practical applications. In this work, we propose a pre-charged membrane potential (PCMP) for the latency reduction in SNN. A variety of neural network applications (e.g., classification, autoencoder using MNIST and CIFAR-10 datasets) are trained and converted to SNNs to demonstrate the effect of the proposed approach. The latency of SNNs is successfully reduced without accuracy loss. In addition, we propose a delayed evaluation method (DE), by which the errors during the initial transient are discarded. The error spikes occurring in the initial transient is removed by DE, resulting in the further latency reduction. DE can be used in combination with PCMP for further latency reduction. Finally, we also show the advantages of the proposed methods in improving the number of spikes required to reach a steady-state of the performance in SNNs for energy-efficient computing.

A thin-layer liquid culture technique for the growth of Helicobacter pylori.

BACKGROUND AND AIMS: Several attempts have been successful in liquid cultivation of Helicobaccter pylori. However, there is a need to improve the growth of H. pylori in liquid media in order to get affluent growth and a simple approach for examining bacterial properties. We introduce here a thin-layer liquid culture technique for the growth of H. pylori. METHODS: A thin-layer liquid culture system was established by adding liquid media to a 90-mm diameter Petri dish. Optimal conditions for bacterial growth were investigated and then viability, growth curve, and released proteins were examined. RESULTS: Maximal growth of H. pylori was obtained by adding 3 mL of brucella broth supplemented with 10% horse to a Petri dish. H. pylori grew in both DMEM and RPMI-1640 supplemented with 10% fetal bovine serum and 0.5% yeast extract. Serum-free RPMI-1640 supported the growth of H. pylori when supplemented with dimethyl-beta-cyclodextrin (200 microg/mL) and 1% yeast extract. Under optimal growth, H. pylori grew exponentially for 28 hours, reaching a density of 3.4 OD(600) with a generation time of 3.3 hours. After 24 hours, cultures at a cell density of 1.0 OD(600) contained 1.3 +/- 0.1 x 10(9 )CFU/mL. gamma-Glutamyl transpeptidase, nuclease, superoxide dismutase, and urease were not detected in culture supernatants at 24 hours in thin-layer liquid culture, but were present at 48 hours, whereas alcohol dehydrogenase, alkylhydroperoxide reductase, catalase, and vacuolating cytotoxin were detected at 24 hours. CONCLUSIONS: Thin-layer liquid culture technique is feasible, and can serve as a versatile liquid culture technique for investigating bacterial properties of H. pylori.

3D AND-Type Stacked Array for Neuromorphic Systems.

NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler-Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level.

Analysis of a Schottky Barrier MOSFET for Synaptic Device Using Hot Carrier Injection.

In this paper, we analyze the hot carrier injection (HCI) in an asymmetric dual-gate structure with a metallic source/drain. We propose a program/erase scheme where HCI occurs on the source side of the body. Owing to the large resistance of the Schottky barrier used, a large electric field is formed around the Schottky barrier. Therefore, impact ionization occurs as the gate voltage is increased and hot carriers are injected into the source side, which is less influenced by the drain voltage. We also analyze the program and erase efficiency by adjusting the Schottky barrier height or by using dopant segregation technique. We expect a small amount of current to flow and great efficiency of the program/erase operations to use as a synaptic device.