Publisher Correction: Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

In this Letter, owing to an error during the production process, the author affiliations were listed incorrectly. Affiliation number 5 (Colleges of Nanoscale Science and Engineering, State University of New York (SUNY)) was repeated, and affiliation numbers 6-8 were incorrect. In addition, the phrase "two oxide thickness variants" should have been "two gate oxide thickness variants". These errors have all been corrected online.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions1,2. This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing3,4. By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip'1,6-8. As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge10,11, this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

Minimum complexity integrated photonic architecture for delay-based reservoir computing.

Reservoir computing is an analog bio-inspired computation scheme for efficiently processing time-dependent signals, the photonic implementations of which promise a combination of massive parallel information processing, low power consumption, and high-speed operation. However, most of these implementations, especially for the case of time-delay reservoir computing, require extensive multi-dimensional parameter optimization to find the optimal combination of parameters for a given task. We propose a novel, largely passive integrated photonic TDRC scheme based on an asymmetric Mach-Zehnder interferometer in a self-feedback configuration, where the nonlinearity is provided by the photodetector, and with only one tunable parameter in the form of a phase shifting element that, as a result of our configuration, allows also to tune the feedback strength, consequently tuning the memory capacity in a lossless manner. Through numerical simulations, we show that the proposed scheme achieves good performance -when compared to other integrated photonic architectures- on the temporal bitwise XOR task and various time series prediction tasks, while greatly reducing hardware and operational complexity.

Single-chip microprocessor that communicates directly using light.

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Monolithic silicon-photonic platforms in state-of-the-art CMOS SOI processes [Invited].

Integrating photonics with advanced electronics leverages transistor performance, process fidelity and package integration, to enable a new class of systems-on-a-chip for a variety of applications ranging from computing and communications to sensing and imaging. Monolithic silicon photonics is a promising solution to meet the energy efficiency, sensitivity, and cost requirements of these applications. In this review paper, we take a comprehensive view of the performance of the silicon-photonic technologies developed to date for photonic interconnect applications. We also present the latest performance and results of our "zero-change" silicon photonics platforms in 45 nm and 32 nm SOI CMOS. The results indicate that the 45 nm and 32 nm processes provide a "sweet-spot" for adding photonic capability and enhancing integrated system applications beyond the Moore-scaling, while being able to offload major communication tasks from more deeply-scaled compute and memory chips without complicated 3D integration approaches.

Ring modulators with enhanced efficiency based on standing-wave operation on a field-matched, interdigitated p-n junction.

We propose ring modulators based on interdigitated p-n junctions that exploit standing rather than traveling-wave resonant modes to improve modulation efficiency, insertion loss and speed. Matching the longitudinal nodes and antinodes of a standing-wave mode with high (contacts) and low (depletion regions) carrier density regions, respectively, simultaneously lowers loss and increases sensitivity significantly. This approach permits further to relax optical constraints on contacts placement and can lead to lower device capacitance. Such structures are well-matched to fabrication in advanced microelectronics CMOS processes. Device architectures that exploit this concept are presented along with their benefits and drawbacks. A temporal coupled mode theory model is used to investigate the static and dynamic response. We show that modulation efficiencies or loss Q factors up to 2 times higher than in previous traveling-wave geometries can be achieved leading to much larger extinction ratios. Finally, we discuss more complex doping geometries that can improve carrier dynamics for higher modulation speeds in this context.