A CMOS BD-BCI: Neural Recorder with Two-Step Time-Domain Quantizer and Multi-Polar Stimulator with Dual-Mode Charge Balancing.

This work presents a bi-directional brain-computer interface (BD-BCI) including a high-dynamic-range (HDR) two-step time-domain neural acquisition (TTNA) system and a high-voltage (HV) multipolar neural stimulation system incorporating dual-mode time-based charge balancing (DTCB) technique. The proposed TTNA includes four independent recording modules that can sense microvolt neural signals while tolerating large stimulation artifacts. In addition, it exhibits an integrated input-referred noise of 2.3 µVrms from 0.1- to 250-Hz and can handle a linear input-signal swing of up to 340 mVPP. The multipolar stimulator is composed of four standalone stimulators each with a maximum current of up to 14 mA (±20-V of voltage compliance) and 8-bit resolution. An inter-channel interference cancellation circuitry is introduced to preserve the accuracy and effectiveness of the DTCB method in the multipolar-stimulation configuration. Fabricated in an HV 180-nm CMOS technology, the BD-BCI chipset undergoes extensive in-vitro and in-vivo evaluations. The recording system achieves a measured SNDR, SFDR, and CMRR of 84.8 dB, 89.6 dB, and >105 dB, respectively. The measurement results verify that the stimulation system is capable of performing high-precision charge balancing with ±2 mV and ±7.5 mV accuracy in the interpulse-bounded time-based charge balancing (TCB) and artifactless TCB modes, respectively.

Benchtop and bedside validation of a low-cost programmable cortical stimulator in a testbed for bi-directional brain-computer-interface research.

Introduction: Bi-directional brain-computer interfaces (BD-BCI) to restore movement and sensation must achieve concurrent operation of recording and decoding of motor commands from the brain and stimulating the brain with somatosensory feedback. Methods: A custom programmable direct cortical stimulator (DCS) capable of eliciting artificial sensorimotor response was integrated into an embedded BCI system to form a safe, independent, wireless, and battery powered testbed to explore BD-BCI concepts at a low cost. The BD-BCI stimulator output was tested in phantom brain tissue by assessing its ability to deliver electrical stimulation equivalent to an FDA-approved commercial electrical cortical stimulator. Subsequently, the stimulator was tested in an epilepsy patient with subcortical electrocorticographic (ECoG) implants covering the sensorimotor cortex to assess its ability to elicit equivalent responses as the FDA-approved counterpart. Additional safety features (impedance monitoring, artifact mitigation, and passive and active charge balancing mechanisms) were also implemeneted and tested in phantom brain tissue. Finally, concurrent operation with interleaved stimulation and BCI decoding was tested in a phantom brain as a proof-of-concept operation of BD-BCI system. Results: The benchtop prototype BD-BCI stimulator's basic output features (current amplitude, pulse frequency, pulse width, train duration) were validated by demonstrating the output-equivalency to an FDA-approved commercial cortical electrical stimulator (R 2 > 0.99). Charge-neutral stimulation was demonstrated with pulse-width modulation-based correction algorithm preventing steady state voltage deviation. Artifact mitigation achieved a 64.5% peak voltage reduction. Highly accurate impedance monitoring was achieved with R 2 > 0.99 between measured and actual impedance, which in-turn enabled accurate charge density monitoring. An online BCI decoding accuracy of 93.2% between instructional cues and decoded states was achieved while delivering interleaved stimulation. The brain stimulation mapping via ECoG grids in an epilepsy patient showed that the two stimulators elicit equivalent responses. Significance: This study demonstrates clinical validation of a fully-programmable electrical stimulator, integrated into an embedded BCI system. This low-cost BD-BCI system is safe and readily applicable as a testbed for BD-BCI research. In particular, it provides an all-inclusive hardware platform that approximates the limitations in a near-future implantable BD-BCI. This successful benchtop/human validation of the programmable electrical stimulator in a BD-BCI system is a critical milestone toward fully-implantable BD-BCI systems.

A Fully-Integrated 1µW/Channel Dual-Mode Neural Data Acquisition System for Implantable Brain-Machine Interfaces.

This paper presents an ultra-low power mixed-signal neural data acquisition (MSN-DAQ) system that enables a novel low-power hybrid-domain neural decoding architecture for implantable brain-machine interfaces with high channel count. Implemented in 180nm CMOS technology, the 32-channel custom chip operates at 1V supply voltage and achieves excellent performance including 1.07µW/channel, 2.37/5.62 NEF/PEF and 88dB common-mode rejection ratio (CMRR) with significant back-end power-saving advantage compared to prior works. The fabricated prototype was further evaluated with in vivo human tests at bedside, and its performance closely follows that of a commercial recording system.

Optimal artifact suppression in simultaneous electrocorticography stimulation and recording for bi-directional brain-computer interface applications.

OBJECTIVE: Electrocorticogram (ECoG)-based brain-computer interfaces (BCIs) are a promising platform for the restoration of motor and sensory functions to those with neurological deficits. Such bi-directional BCI operation necessitates simultaneous ECoG recording and stimulation, which is challenging given the presence of strong stimulation artifacts. This problem is exacerbated if the BCI's analog front-end operates in an ultra-low power regime, which is a basic requirement for fully implantable medical devices. In this study, we developed a novel method for the suppression of stimulation artifacts before they reach the analog front-end. APPROACH: Using elementary biophysical considerations, we devised an artifact suppression method that employs a weak auxiliary stimulation delivered between the primary stimulator and the recording grid. The exact location and amplitude of this auxiliary stimulating dipole were then found through a constrained optimization procedure. The performance of our method was tested in both simulations and phantom brain tissue experiments. MAIN RESULTS: The solution found through the optimization procedure matched the optimal canceling dipole in both simulations and experiments. Artifact suppression as large as 28.7 dB and 22.9 dB were achieved in simulations and brain phantom experiments, respectively. SIGNIFICANCE: We developed a simple constrained optimization-based method for finding the parameters of an auxiliary stimulating dipole that yields optimal artifact suppression. Our method suppresses stimulation artifacts before they reach the analog front-end and may prevent the front-end amplifiers from saturation. Additionally, it can be used along with other artifact mitigation techniques to further reduce stimulation artifacts.

An Energy-Efficient CMOS Dual-Mode Array Architecture for High-Density ECoG-Based Brain-Machine Interfaces.

This article presents an energy-efficient electrocorticography (ECoG) array architecture for fully-implantable brain machine interface systems. A novel dual-mode analog signal processing method is introduced that extracts neural features from high- γ band (80-160 Hz) at the early stages of signal acquisition. Initially, brain activity across the full-spectrum is momentarily observed to compute the feature weights in the digital back-end during full-band mode operation. Subsequently, these weights are fed back to the front-end and the system reverts to base-band mode to perform feature extraction. This approach utilizes a distinct optimized signal pathway based on power envelope extraction, resulting in 1.72× power reduction in the analog blocks and up to 50× potential power savings for digitization and processing (implemented off-chip in this article). A prototype incorporating a 32-channel ultra-low power signal acquisition front-end is fabricated in 180 nm CMOS process with 0.8 V supply. This chip consumes 1.05  µW (0.205  µW for feature extraction only) power and occupies 0.245 [Formula: see text] die area per channel. The chip measurement shows better than 76.5-dB common-mode rejection ratio (CMRR), 4.09 noise efficiency factor (NEF), and 10.04 power efficiency factor (PEF). In-vivo human tests have been carried out with electroencephalography and ECoG signals to validate the performance and dual-mode operation in comparison to commercial acquisition systems.