Publisher Correction: Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

In this Letter, owing to an error during the production process, the author affiliations were listed incorrectly. Affiliation number 5 (Colleges of Nanoscale Science and Engineering, State University of New York (SUNY)) was repeated, and affiliation numbers 6-8 were incorrect. In addition, the phrase "two oxide thickness variants" should have been "two gate oxide thickness variants". These errors have all been corrected online.

Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions1,2. This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing3,4. By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip'1,6-8. As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge10,11, this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

Single-chip microprocessor that communicates directly using light.

Data transport across short electrical wires is limited by both bandwidth and power density, which creates a performance bottleneck for semiconductor microchips in modern computer systems--from mobile phones to large-scale data centres. These limitations can be overcome by using optical communications based on chip-scale electronic-photonic systems enabled by silicon-based nanophotonic devices. However, combining electronics and photonics on the same chip has proved challenging, owing to microchip manufacturing conflicts between electronics and photonics. Consequently, current electronic-photonic chips are limited to niche manufacturing processes and include only a few optical devices alongside simple circuits. Here we report an electronic-photonic system on a single chip integrating over 70 million transistors and 850 photonic components that work together to provide logic, memory, and interconnect functions. This system is a realization of a microprocessor that uses on-chip photonic devices to directly communicate with other chips using light. To integrate electronics and photonics at the scale of a microprocessor chip, we adopt a 'zero-change' approach to the integration of photonics. Instead of developing a custom process to enable the fabrication of photonics, which would complicate or eliminate the possibility of integration with state-of-the-art transistors at large scale and at high yield, we design optical devices using a standard microelectronics foundry process that is used for modern microprocessors. This demonstration could represent the beginning of an era of chip-scale electronic-photonic systems with the potential to transform computing system architectures, enabling more powerful computers, from network infrastructure to data centres and supercomputers.

Ring modulators with enhanced efficiency based on standing-wave operation on a field-matched, interdigitated p-n junction.

We propose ring modulators based on interdigitated p-n junctions that exploit standing rather than traveling-wave resonant modes to improve modulation efficiency, insertion loss and speed. Matching the longitudinal nodes and antinodes of a standing-wave mode with high (contacts) and low (depletion regions) carrier density regions, respectively, simultaneously lowers loss and increases sensitivity significantly. This approach permits further to relax optical constraints on contacts placement and can lead to lower device capacitance. Such structures are well-matched to fabrication in advanced microelectronics CMOS processes. Device architectures that exploit this concept are presented along with their benefits and drawbacks. A temporal coupled mode theory model is used to investigate the static and dynamic response. We show that modulation efficiencies or loss Q factors up to 2 times higher than in previous traveling-wave geometries can be achieved leading to much larger extinction ratios. Finally, we discuss more complex doping geometries that can improve carrier dynamics for higher modulation speeds in this context.

Wavelength conversion in modulated coupled-resonator systems and their design via an equivalent linear filter representation.

We propose wavelength converters based on modulated coupled resonators that achieve conversion by matching the modulation frequency to the frequency splitting of the supermodes of the unmodulated system. Using temporal coupled-mode theory, we show that these time-variant systems have an equivalent linear, time-invariant filter representation that simplifies the optimal engineering of design parameters for realistic systems. Applying our model to carrier plasma-dispersion modulators as an example implementation, we calculate conversion efficiencies between -5.4 and -1.7 dB for intrinsic quality factors of 10(4)-10(6). We show that the ratio of the resonance shift to the total linewidth is the most important parameter when determining conversion efficiency. Finally, we discuss how this model can be used to design devices such as frequency shifters, widely tunable radio frequency oscillators, and frequency combs.

Channel add-drop filter based on dual photonic crystal cavities in push-pull mode.

We demonstrate an add-drop filter based on a dual photonic crystal nanobeam cavity system that emulates the operation of a traveling wave resonator, and, thus, provides separation of the through and drop port transmission from the input port. The device is on a 3×3 mm chip fabricated in an advanced microelectronics silicon-on-insulator complementary metal-oxide semiconductor (SOI CMOS) process (IBM 45 nm SOI) without any foundry process modifications. The filter shows 1 dB of insertion loss in the drop port with a 3 dB bandwidth of 64 GHz, and 16 dB extinction in the through port. To the best of our knowledge, this is the first implementation of a port-separating, add-drop filter based on standing wave cavities coupled to conventional waveguides, and demonstrates a performance that suggests potential for photonic crystal devices within optical immersion lithography-based advanced CMOS electronics-photonics integration.

Efficient wavelength multiplexers based on asymmetric response filters.

We propose integrated photonic wavelength multiplexers based on serially cascaded channel add-drop filters with an asymmetric frequency response. By utilizing the through-port rejection of the previous channel to advantage, the asymmetric response provides optimal rejection of the adjacent channels at each wavelength channel. We show theoretically the basic requirements to realize an asymmetric filter response, and propose and evaluate the possible implementations using coupled resonators. For one implementation, we provide detailed design formulas based on a coupled-mode theory model, and more generally we provide broad guidelines that enumerate all structures that can provide asymmetric passbands in the context of a pole-zero design approach to engineering the device response. Using second-order microring resonator filter stages as an example, we show that the asymmetric multiplexer can provide 2.4 times higher channel packing (bandwidth) density than a multiplexer using the same order stages (number of resonators) using conventional all-pole maximally-flat designs. We also address the sensitivities and constraints of various implementations of our proposed approach, as it affects their applicability to CMOS photonic interconnects.

Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS.

We demonstrate the first (to the best of our knowledge) depletion-mode carrier-plasma optical modulator fabricated in a standard advanced complementary metal-oxide-semiconductor (CMOS) logic process (45 nm node SOI CMOS) with no process modifications. The zero-change CMOS photonics approach enables this device to be monolithically integrated into state-of-the-art microprocessors and advanced electronics. Because these processes support lateral p-n junctions but not efficient ridge waveguides, we accommodate these constraints with a new type of resonant modulator. It is based on a hybrid microring/disk cavity formed entirely in the sub-90 nm thick monocrystalline silicon transistor body layer. Electrical contact of both polarities is made along the inner radius of the multimode ring cavity via an array of silicon spokes. The spokes connect to p and n regions formed using transistor well implants, which form radially extending lateral junctions that provide index modulation. We show 5 Gbps data modulation at 1265 nm wavelength with 5.2 dB extinction ratio and an estimated 40 fJ/bit energy consumption. Broad thermal tuning is demonstrated across 3.2 THz (18 nm) with an efficiency of 291 GHz/mW. A single postprocessing step to remove the silicon handle wafer was necessary to support low-loss optical confinement in the device layer. This modulator is an important step toward monolithically integrated CMOS photonic interconnects.

Depletion-mode polysilicon optical modulators in a bulk complementary metal-oxide semiconductor process.

We demonstrate depletion-mode carrier-plasma optical modulators fabricated in a bulk complementary metal-oxide semiconductor (CMOS), DRAM-emulation process. To the best of our knowledge, these are the first depletion-mode modulators demonstrated in polycrystalline silicon and in bulk CMOS. The modulators are based on novel optical microcavities that utilize periodic spatial interference of two guided modes to create field nulls along waveguide sidewalls. At these nulls, electrical contacts can be placed while preserving a high optical Q. These cavities enable active devices in a process with no partial silicon etch and with lateral p-n junctions. We demonstrate two device variants at 5 Gbps data modulation rate near 1610 nm wavelength. One design shows 3.1 dB modulation depth with 1.5 dB insertion loss and an estimated 160 fJ/bit energy consumption, while a more compact device achieves 4.2 dB modulation depth with 4.0 dB insertion loss and 60 fJ/bit energy consumption. These modulators represent a significant breakthrough in enabling active photonics in bulk silicon CMOS--the platform of the majority of microelectronic logic and DRAM processes--and lay the groundwork for monolithically integrated CMOS-to-DRAM photonic links.