Universal dimension reduced phase compensation algorithm for an optical phased array.

Optical phased arrays (OPAs) can achieve non-mechanical beam deflection. Many types of OPA face the problem of low deflection efficiency due to the phase distortion induced by mutual coupling between nearby channels. In this Letter, a universal optimization algorithm is proposed to compensate for this structural phase distortion, in which the adjacent sampling principal component analysis (AS-PCA) method is introduced to reduce the dimension of the solution space. Simulations and experimental results on different classes of OPA verified that this method can considerably optimize the deflection beam with a rapid convergence speed, irrespective of the scale of OPA, and maintain the universal feature, laying the foundation for large-scale, high-density OPA in-line optimization. We envision it to become a general method on different platforms.

Fast, closed-loop iterative system-on-chip of deflection efficiency enhancement for a liquid crystal optical phased array.

To implement a liquid crystal optical phased array (LC-OPA) on a practical free-space laser communication terminal, there are two essential parameters: insertion loss and the closed-loop bandwidth required to meet the dynamic linking condition of the acquisition-tracking-pointing sub-system. Real-time hardware platforms and deflection efficiency optimization algorithms have been suggested since the invention of LC-OPA. In this paper, the so-called ZYNQ platform, a field-programmable-gate-array-based heterogeneous system-on-chip (SoC), is utilized to keep real-time response and accelerate data generation, such as beam steering, beamforming, beam enhancement, etc. In addition, a novel, to the best of our knowledge, optimization algorithm is proposed on the concept of dimension reduction of the number of objective variables. After deploying on this heterogeneous SoC platform, numerical simulations and experimental results both verify that, compared to the conventional PC-based system, the integrated SoC platform offers 15.8 times faster iterative speed, a rapid convergence rate, and excellent robustness, yet with less usage of power, physical size, and monetary cost. The efficiency enhancement process costs only a few seconds at any angle, laying the foundation for practical in-line applications.