'Memristive' switches enable 'stateful' logic operations via material implication.

The authors of the International Technology Roadmap for Semiconductors-the industry consensus set of goals established for advancing silicon integrated circuit technology-have challenged the computing research community to find new physical state variables (other than charge or voltage), new devices, and new architectures that offer memory and logic functions beyond those available with standard transistors. Recently, ultra-dense resistive memory arrays built from various two-terminal semiconductor or insulator thin film devices have been demonstrated. Among these, bipolar voltage-actuated switches have been identified as physical realizations of 'memristors' or memristive devices, combining the electrical properties of a memory element and a resistor. Such devices were first hypothesized by Chua in 1971 (ref. 15), and are characterized by one or more state variables that define the resistance of the switch depending upon its voltage history. Here we show that this family of nonlinear dynamical memory devices can also be used for logic operations: we demonstrate that they can execute material implication (IMP), which is a fundamental Boolean logic operation on two variables p and q such that pIMPq is equivalent to (NOTp)ORq. Incorporated within an appropriate circuit, memristive switches can thus perform 'stateful' logic operations for which the same devices serve simultaneously as gates (logic) and latches (memory) that use resistance instead of voltage or charge as the physical state variable.

A hybrid nanomemristor/transistor logic circuit capable of self-programming.

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing.

Observation of two resistance switching modes in TiO2 memristive devices electroformed at low current.

We report the observation of two resistance switching modes in certain 50 nm × 50 nm crossbar TiO(2) memristive devices that have been electroformed with a low-current process. The two switching modes showed opposite switching polarities. The intermediate state was shared by both modes (the ON state of the high-resistance mode or the OFF state of the low-resistance mode) and exhibited a relaxation to a more resistive state, including an initial transient decay. The activation energies of such a decay and ON-switching to the intermediate state were determined to be 50-210 meV and 1.1 eV, respectively. Although they are attributed to the coexistence of charge trapping and ionic motion, the ionic motion dominates in both switching modes. Our results indicate that the two switching modes in our system correspond to different switching layers adjacent to the interfaces at the top and bottom electrodes.

The switching location of a bipolar memristor: chemical, thermal and structural mapping.

Memristors are memory resistors promising a rapid integration into future memory technologies. However, progress is still critically limited by a lack of understanding of the physical processes occurring at the nanoscale. Here we correlate device electrical characteristics with local atomic structure, chemistry and temperature. We resolved a single conducting channel that is made up of a reduced phase of the as-deposited titanium oxide. Moreover, we observed sufficient Joule heating to induce a crystallization of the oxide surrounding the channel, with a peculiar pattern that finite element simulations correlated with the existence of a hot spot close to the bottom electrode, thus identifying the switching location. This work reports direct observations in all three dimensions of the internal structure of titanium oxide memristors.

Impact of geometry on the performance of memristive nanodevices.

We examined the influence of memristor geometry on switching endurance by comparing ribbed and planar TiO(2)-based cross-point devices with 50 nm × 50 nm lateral dimensions. We observed that planar devices exhibited a factor of over four improvement in median endurance value over ribbed structures for otherwise identical structures. Our simulations indicated that the corners in the upper wires of the ribbed devices experienced higher current density and more heating during device forming and switching, and hence a shorter life time.

A memristor-based nonvolatile latch circuit.

Memristive devices, which exhibit a dynamical conductance state that depends on the excitation history, can be used as nonvolatile memory elements by storing information as different conductance states. We describe the implementation of a nonvolatile synchronous flip-flop circuit that uses a nanoscale memristive device as the nonvolatile memory element. Controlled testing of the circuit demonstrated successful state storage and restoration, with an error rate of 0.1%, during 1000 power loss events. These results indicate that integration of digital logic devices and memristors could open the way for nonvolatile computation with applications in small platforms that rely on intermittent power sources. This demonstrated feasibility of tight integration of memristors with CMOS (complementary metal-oxide-semiconductor) circuitry challenges the traditional memory hierarchy, in which nonvolatile memory is only available as a large, slow, monolithic block at the bottom of the hierarchy. In contrast, the nonvolatile, memristor-based memory cell can be fast, fine-grained and small, and is compatible with conventional CMOS electronics. This threatens to upset the traditional memory hierarchy, and may open up new architectural possibilities beyond it.

Coupled ionic and electronic transport model of thin-film semiconductor memristive behavior.

The memristor, the fourth passive circuit element, was predicted theoretically nearly 40 years ago, but we just recently demonstrated both an intentional material system and an analytical model that exhibited the properties of such a device. Here we provide a more physical model based on numerical solutions of coupled drift-diffusion equations for electrons and ions with appropriate boundary conditions. We simulate the dynamics of a two-terminal memristive device based on a semiconductor thin film with mobile dopants that are partially compensated by a small amount of immobile acceptors. We examine the mobile ion distributions, zero-bias potentials, and current-voltage characteristics of the model for both steady-state bias conditions and for dynamical switching to obtain physical insight into the transport processes responsible for memristive behavior in semiconductor films.