Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs.

In this study, we report a low ohmic contact resistance process on a 650 V E-mode p-GaN gate HEMT structure. An amorphous silicon (a-Si) assisted layer was inserted in between the ohmic contact and GaN. The fabricated device exhibits a lower contact resistance of about 0.6 Ω-mm after annealing at 550 °C. In addition, the threshold voltage shifting of the device was reduced from -0.85 V to -0.74 V after applying a high gate bias stress at 150 °C for 10-2 s. The measured time to failure (TTF) of the device shows that a low thermal budget process can improve the device's reliability. A 100-fold improvement in HTGB TTF was clearly demonstrated. The study shows a viable method for CMOS-compatible GaN power device fabrication.

Embedded Integration of Sb2Se3 Film by Low-Temperature Plasma-Assisted Chemical Vapor Reaction with Polycrystalline Si Transistor for High-Performance Flexible Visible-to-Near-Infrared Photodetector.

Flexible optoelectronics have garnered considerable interest for applications such as optical communication, motion capture, biosignal detection, and night vision. Transition-metal dichalcogenides are widely used as flexible photodetectors owing to their outstanding electrical and optical properties and high flexibility. Herein, a two-dimensional (2D) Sb2Se3 film-based one transistor-one resistor (1T1R) flexible photodetector with high photosensing current and detection ranges from visible to near-infrared was developed. The flexible 1T1R was fabricated using an efficient field-effect transistor platform with the 2D Sb2Se3 film directly deposited on the sensing region using a low-temperature plasma-assisted chemical vapor reaction. The photodetector could achieve a maximum Iphoto/Idark of 15,000 under white light with a power density of 26 mW/cm2, in which the photodetector showed quick rising and falling response times of 0.16 and 0.28 s, respectively. The 2D Sb2Se3 film exhibits broadband absorption in the visible and IR regions, yielding an excellent photoresponse under laser illumination with different wavelengths. To investigate the flexibility and stability of the 1T1R photodetector, the photoresponses were measured under different bending cycles and curvatures, which maintained its functions and exhibited high stability under convex and concave bending at a curvature radius of 20 mm.

Low-Temperature Growth of Hydrogenated Amorphous Silicon Carbide Solar Cell by Inductively Coupled Plasma Deposition Toward High Conversion Efficiency in Indoor Lighting.

A p-a-SiC:H window layer was used in amorphous Si thin film solar cells to boost the conversion efficiency in an indoor lighting of 500 lx. The p-a-SiC:H window layer/p-a-Si:H buffer layer scheme moderates the abrupt band bending across the p/i interface for the enhancement of VOC, JSC and FF in the solar spectra of short wavelengths. The optimized thickness of i-a-Si:H absorber layer is 400 nm to achieve the conversion efficiency of ~9.58% in an AM1.5 G solar spectrum. However, the optimized thickness of the absorber layer can be changed from 400 to 600 nm in the indoor lighting of 500 lx, exhibiting the maximum output power of 25.56 µW/cm2. Furthermore, various durability tests with excellent performance were investigated, which are significantly beneficial to harvest the indoor lights for applications in the self-powered internet of thing (IoT).

High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits.

Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (Ion)/subthreshold swing (S.S.) of 181 µA/µm/107 mV/dec and 188 µA/µm/98 mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390 mV at VDD = 1.0 V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate.

Performance Characterization of Dye-Sensitized Photovoltaics under Indoor Lighting.

Indoor utilization of emerging photovoltaics is promising; however, efficiency characterization under room lighting is challenging. We report the first round-robin interlaboratory study of performance measurement for dye-sensitized photovoltaics (cells and mini-modules) and one silicon solar cell under a fluorescent dim light. Among 15 research groups, the relative deviation in power conversion efficiency (PCE) of the samples reaches an unprecedented 152%. On the basis of the comprehensive results, the gap between photometry and radiometry measurements and the response of devices to the dim illumination are identified as critical obstacles to the correct PCE. Therefore, we use an illuminometer as a prime standard with a spectroradiometer to quantify the intensity of indoor lighting and adopt the reverse-biased current-voltage (I-V) characteristics as an indicator to qualify the I-V sampling time for dye-sensitized photovoltaics. The recommendations can brighten the prospects of emerging photovoltaics for indoor applications.