Low-current operations in 4F(2)-compatible Ta2O5-based complementary resistive switches.

Complementary resistive switches (CRS), which consist of two anti-serially connected bipolar switching ReRAM cells, can reduce sneak path currents in passive crossbar arrays. However, the high operation current restrains the implementation of the CRS device. In this article, we present low current operation (<300 µA) of vertically stacked, 4F(2)-compatible Ta2O5-based CRS devices exhibiting two terminals. Two types of devices, either offering a nano- or a micrometer scale bottom cell (BC), are considered. The top cell (TC) in both configurations is designed of micrometer size. A novel three-step electroforming procedure for the vertical CRS device having no access to the middle electrode is exemplified and compared to the conventional forming procedure using three-terminal CRS devices. This three-step electroforming procedure provides adjustment of the maximum switching current in the nano-BC CRS: a low-level current compliance during forming enables low current CRS operation in subsequent switching cycles. Further, the nano-BC CRS shows the stable switching up to 10(4) cycles whereas the micro-BC CRS endures up to 10(6) cycles.

Volatile resistance states in electrochemical metallization cells enabling non-destructive readout of complementary resistive switches.

Redox-based resistive memory cells exhibit changes of OFF or intermediate resistance values over time and even ON states can be completely lost in certain cases. The stability of these resistance states and the time until resistance loss strongly depends on the materials system. On the basis of electrical measurements and chemical analysis we found a viable explanation for these volatile resistance states (VRSs) in Ag-GeSx-based electrochemical metallization memory cells and identified a technological application in the field of crossbar memories. Complementary resistive switches usually suffer from the necessity of a destructive read-out procedure increasing wear and reducing read-out speed. From our analysis we deduced a solution to use the VRS as an inherent selector mechanism without the need for additional selector devices.

Complementary resistive switches for passive nanocrossbar memories.

On the road towards higher memory density and computer performance, a significant improvement in energy efficiency constitutes the dominant goal in future information technology. Passive crossbar arrays of memristive elements were suggested a decade ago as non-volatile random access memories (RAM) and can also be used for reconfigurable logic circuits. As such they represent an interesting alternative to the conventional von Neumann based computer chip architectures. Crossbar architectures hold the promise of a significant reduction in energy consumption because of their ultimate scaling potential and because they allow for a local fusion of logic and memory, thus avoiding energy consumption by data transfer on the chip. However, the expected paradigm change has not yet taken place because the general problem of selecting a designated cell within a passive crossbar array without interference from sneak-path currents through neighbouring cells has not yet been solved satisfactorily. Here we introduce a complementary resistive switch. It consists of two antiserial memristive elements and allows for the construction of large passive crossbar arrays by solving the sneak path problem in combination with a drastic reduction of the power consumption.

Realization of Minimum and Maximum Gate Function in Ta2O5-based Memristive Devices.

Redox-based resistive switching devices (ReRAM) are considered key enablers for future non-volatile memory and logic applications. Functionally enhanced ReRAM devices could enable new hardware concepts, e.g. logic-in-memory or neuromorphic applications. In this work, we demonstrate the implementation of ReRAM-based fuzzy logic gates using Ta2O5 devices to enable analogous Minimum and Maximum operations. The realized gates consist of two anti-serially connected ReRAM cells offering two inputs and one output. The cells offer an endurance up to 10(6) cycles. By means of exemplary input signals, each gate functionality is verified and signal constraints are highlighted. This realization could improve the efficiency of analogous processing tasks such as sorting networks in the future.

Multistate Memristive Tantalum Oxide Devices for Ternary Arithmetic.

Redox-based resistive switching random access memory (ReRAM) offers excellent properties to implement future non-volatile memory arrays. Recently, the capability of two-state ReRAMs to implement Boolean logic functionality gained wide interest. Here, we report on seven-states Tantalum Oxide Devices, which enable the realization of an intrinsic modular arithmetic using a ternary number system. Modular arithmetic, a fundamental system for operating on numbers within the limit of a modulus, is known to mathematicians since the days of Euclid and finds applications in diverse areas ranging from e-commerce to musical notations. We demonstrate that multistate devices not only reduce the storage area consumption drastically, but also enable novel in-memory operations, such as computing using high-radix number systems, which could not be implemented using two-state devices. The use of high radix number system reduces the computational complexity by reducing the number of needed digits. Thus the number of calculation operations in an addition and the number of logic devices can be reduced.

Ag/GeSx/Pt-based complementary resistive switches for hybrid CMOS/nanoelectronic logic and memory architectures.

Complementary resistive switches based on two anti-serially connected Ag/GeSx/Pt devices were studied. The main focus was placed on the pulse mode properties as typically required in memory and logic applications. A self-designed measurement setup was applied to access each CRS part-cell individually. Our findings reveal the existence of two distinct read voltage regimes enabling both spike read as well as level read approaches. Furthermore, we experimentally verified the theoretically predicted kinetic properties in terms of pulse height vs. switching time relationship. The results obtained by this alternative approach allow a significant improvement of the basic understanding of the interplay between the two part-cells in a complementary resistive switch configuration. Furthermore, from these observations we can deduce a simplified write voltage scheme which is applicable for the considered type of memory cell.

An associative capacitive network based on nanoscale complementary resistive switches for memory-intensive computing.

We report on the implementation of an Associative Capacitive Network (ACN) based on the nondestructive capacitive readout of two Complementary Resistive Switches (2-CRSs). ACNs are capable of performing a fully parallel search for Hamming distances (i.e. similarity) between input and stored templates. Unlike conventional associative memories where charge retention is a key function and hence, they require frequent refresh cycles, in ACNs, information is retained in a nonvolatile resistive state and normal tasks are carried out through capacitive coupling between input and output nodes. Each device consists of two CRS cells and no selective element is needed, therefore, CMOS circuitry is only required in the periphery, for addressing and read-out. Highly parallel processing, nonvolatility, wide interconnectivity and low-energy consumption are significant advantages of ACNs over conventional and emerging associative memories. These characteristics make ACNs one of the promising candidates for applications in memory-intensive and cognitive computing, switches and routers as binary and ternary Content Addressable Memories (CAMs) and intelligent data processing.