RESUMO
2D materials with atomic thickness display strong gate controllability and emerge as promising materials to build area-efficient electronic circuits. However, achieving the effective and nondestructive modulation of carrier density/type in 2D materials is still challenging because the introduction of dopants will greatly degrade the carrier transport via Coulomb scattering. Here, a strategy to control the polarity of tungsten diselenide (WSe2 ) field-effect transistors (FETs) via introducing hexagonal boron nitride (h-BN) as the interfacial dielectric layer is devised. By modulating the h-BN thickness, the carrier type of WSe2 FETs has been switched from hole to electron. The ultrathin body of WSe2 , combined with the effective polarity control, together contribute to the versatile single-transistor logic gates, including NOR, AND, and XNOR gates, and the operation of only two transistors as a half adder in logic circuits. Compared with the use of 12 transistors based on static Si CMOS technology, the transistor number of the half adder is reduced by 83.3%. The unique carrier modulation approach has general applicability toward 2D logic gates and circuits for the improvement of area efficiency in logic computation.
RESUMO
Two-dimensional (2D) semiconductors have been considered as promising candidates to fabricate ultimately scaled field-effect transistors (FETs), due to the atomically thin thickness and high carrier mobility. However, the performance of FETs based on 2D semiconductors has been limited by extrinsic factors, including high contact resistance, strong interfacial scattering, and unintentional doping. Among these challenges, contact resistance is a dominant issue, and important progress has been made in recent years. In this review, the Schottky-Mott model is introduced to show the ideal Schottky barrier, and we further discuss the contribution of the Fermi-level pinning effect to the high contact resistance in 2D semiconductor devices. In 2D FETs, Fermi-level pinning is attributed to the high-energy metal deposition process, which would damage the lattice of atomically thin 2D semiconductors and induce the pinning of the metal Fermi level. Then, two contact structures and the strategies to fabricate low-contact-resistance short-channel 2D FETs are introduced. Finally, our review provides practical guidelines for the realization of high-performance 2D-semiconductors-based FETs with low contact resistance and discusses the outlook of this field.
RESUMO
Two-dimensional (2D) materials with the atomically thin thickness have attracted great interest in the post-Moore's Law era because of their tremendous potential to continue transistor downscaling and offered advances in device performance at the atomic limit. However, the metal-semiconductor contact is the bottleneck in field-effect transistors (FETs) integrating 2D semiconductors as channel materials. A robust and tunable doping method at the source and drain region of 2D transistors to minimize the contact resistance is highly sought after. Here we report a stable carrier doping method via the mild covalent grafting of maleimides on the surface of 2D transition metal dichalcogenides. The chemisorbed interaction contributes to the efficient carrier doping without degrading the high-performance carrier transport. Density functional theory results further illustrate that the molecular functionalization leads to the mild hybridization and the negligible impact on the conduction bands of monolayer MoS2, avoiding the random scattering from the dopants. Differently from reported molecular treatments, our strategy displays high thermal stability (above 300 °C) and it is compatible with micro/nano processing technology. The contact resistance of MoS2 FETs can be greatly reduced by â¼12 times after molecular functionalization. The Schottky barrier of 44 meV is achieved on monolayer MoS2 FETs, demonstrating efficient charge injection between metal and 2D semiconductor. The mild covalent functionalization of molecules on 2D semiconductors represents a powerful strategy to perform the carrier doping and the device optimization.