Metasurfaces on silicon photonic waveguides for simultaneous emission phase and amplitude control.

Chip-scale photonic systems that manipulate free-space emission have recently attracted attention for applications such as free-space optical communications and solid-state LiDAR. Silicon photonics, as a leading platform for chip-scale integration, needs to offer more versatile control of free-space emission. Here we integrate metasurfaces on silicon photonic waveguides to generate free-space emission with controlled phase and amplitude profiles. We demonstrate experimentally structured beams, including a focused Gaussian beam and a Hermite-Gaussian TEM10 beam, as well as holographic image projections. Our approach is monolithic and CMOS-compatible. The simultaneous phase and amplitude control enable more faithful generation of structured beams and speckle-reduced projection of holographic images.

I-line photolithographic metalenses enabled by distributed optical proximity correction with a deep-learning model.

High pattern fidelity is paramount to the performance of metalenses and metasurfaces, but is difficult to achieve using economic photolithography technologies due to low resolutions and limited process windows of diverse subwavelength structures. These hurdles can be overcome by photomask sizing or reshaping, also known as optical proximity correction (OPC). However, the lithographic simulators critical to model-based OPC require precise calibration and have not yet been specifically developed for metasurface patterning. Here, we demonstrate an accurate lithographic model based on Hopkin's image formulation and fully convolutional networks (FCN) to control the critical dimension (CD) patterning of a near-infrared (NIR) metalens through a distributed OPC flow using i-line photolithography. The lithographic model achieves an average ΔCD/CD = 1.69% due to process variations. The model-based OPC successfully produces the 260 nm CD in a metalens layout, which corresponds to a lithographic constant k1 of 0.46 and is primarily limited by the resolution of the photoresist. Consequently, our fabricated NIR metalens with a diameter of 1.5 mm and numerical aperture (NA) of 0.45 achieves a measured focusing efficiency of 64%, which is close to the calculated value of 69% and among the highest reported values using i-line photolithography.

Approaching conversion limit with all-dielectric solar cell reflectors.

Metallic back reflectors has been used for thin-film and wafer-based solar cells for very long time. Nonetheless, the metallic mirrors might not be the best choices for photovoltaics. In this work, we show that solar cells with all-dielectric reflectors can surpass the best-configured metal-backed devices. Theoretical and experimental results all show that superior large-angle light scattering capability can be achieved by the diffuse medium reflectors, and the solar cell J-V enhancement is higher for solar cells using all-dielectric reflectors. Specifically, the measured diffused scattering efficiency (D.S.E.) of a diffuse medium reflector is >0.8 for the light trapping spectral range (600nm-1000nm), and the measured reflectance of a diffuse medium can be as high as silver if the geometry of embedded titanium oxide(TiO(2)) nanoparticles is optimized. Moreover, the diffuse medium reflectors have the additional advantage of room-temperature processing, low cost, and very high throughput. We believe that using all-dielectric solar cell reflectors is a way to approach the thermodynamic conversion limit by completely excluding metallic dissipation.

Meta-Learned and TCAD-Assisted Sampling in Semiconductor Laser Annealing.

While applying machine learning (ML) to semiconductor manufacturing is prevalent, an efficient way to sample the search space has not been explored much in key processes such as lithography, annealing, deposition, and etching. The aim is to use the fewest experimental trials to construct an accurate predictive model. Here, we proposed a technology computer added design (TCAD)-assisted meta-learned sampling approach. The meta-learner adjusts the way of sampling in terms of how to hybridize the TCAD with ML when selecting the next sampling point. While an advanced semiconductor process is expensive, efficient sampling is indispensable. Using laser annealing as an example, we demonstrate the effectiveness of the proposed algorithm where the mean square error (MSE) at the first 100 sampling steps using TCAD-assisted meta-learned sampling is significantly lower than the pure ML approach. Besides, with reference to the pure TCAD approach, the TCAD-assisted sampling prevents the MSE degradation at 200-400 sampling steps. The proposed approach can be used in other manufacturing or even any applied machine intelligence fields.

Dual-mode frequency multiplier in graphene-base hot electron transistor.

Since quantum computers have been gradually introduced in countries around the world, the development of the many related quantum components that can operate independently of temperature has become more important for enabling mature products with low power dissipation and high efficiency. As an alternative to studying cryo-CMOSs (complementary metal-oxide-semiconductors) to achieve this goal, quantum tunneling devices based on 2D materials can be examined instead. In this work, a vertical graphene-based quantum tunneling transistor has been used as a frequency modulator. The transistor can operate via different quantum tunneling mechanisms and generates, by applying the appropriate bias, voltage-resistance curves characteristic of variable nonlinear resistance for both base and emitter voltages. We experimentally demonstrate frequency modulation from input signals over the range of 100 kHz to 10 MHz, enabling a tunable frequency doubler or tripler in just a single transistor. This frequency multiplication with a tunneling mechanism makes the graphene-based tunneling device a promising option for frequency electronics in the emerging field of quantum technologies.

Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs.

In this study, we report a low ohmic contact resistance process on a 650 V E-mode p-GaN gate HEMT structure. An amorphous silicon (a-Si) assisted layer was inserted in between the ohmic contact and GaN. The fabricated device exhibits a lower contact resistance of about 0.6 Ω-mm after annealing at 550 °C. In addition, the threshold voltage shifting of the device was reduced from -0.85 V to -0.74 V after applying a high gate bias stress at 150 °C for 10-2 s. The measured time to failure (TTF) of the device shows that a low thermal budget process can improve the device's reliability. A 100-fold improvement in HTGB TTF was clearly demonstrated. The study shows a viable method for CMOS-compatible GaN power device fabrication.

Passivated Interfacial Traps of Monolayer MoS2 with Bipolar Electrical Pulse.

Heterogeneous integration of monolayers is an emergent route of spatially combining materials with available platforms for unprecedented properties. A long-standing challenge along this route is to manipulate interfacial configurations of each unit in stacking architecture. A monolayer of transition metal dichalcogenides (TMDs) offers an embodiment of studying interface engineering of integrated systems because optoelectronic performances generally trade off with each other due to interfacial trap states. While ultrahigh photoresponsivity of TMDs phototransistors has been realized, a long response time commonly appears and hinders applications. Here, fundamental processes in excitation and relaxation of the photoresponse are studied and correlated with interfacial traps of the monolayer MoS2. A mechanism for the onset of saturation photocurrent and the reset behavior in the monolayer photodetector is illustrated based on device performances. Electrostatic passivation of interfacial traps is achieved with the bipolar gate pulse and significantly reduces the response time for photocurrent to reach saturated states. This work paves the way toward fast-speed and ultrahigh-gain devices of stacked two-dimensional monolayers.

Nano-patterned glass superstrates with different aspect ratios for enhanced light harvesting in a-Si:H thin film solar cells.

Nano-patterned glass superstrates obtained via a large-area production approach are desirable for antireflection and light trapping in thin-film solar cells. The tapered nanostructures allow a graded refractive index profile between the glass and material interfaces, leading to suppressed surface reflection and increased forward diffraction of light. In this work, we investigate nanostructured glass patterns with different aspect ratios using scalable nanosphere lithography for hydrogenated amorphous silicon (a-Si:H) thin film solar cells. Compared to flat glass cell and Asahi U-type glass cell, enhancements in short-circuit current density (J(sc)) of 51.6% and 8%, respectively, were achieved for a moderate aspect ratio of 0.16. The measured external quantum efficiencies (EQE) spectra confirmed a broadband enhancement due to antireflection and light trapping properties.

Design, fabrication, and characterization of Si-based ARROW photonic crystal bend waveguides and power splitters.

Silicon-based (Si-based) photonic crystal waveguide based on antiresonant reflecting optical waveguide (ARROW PCW) structures consisting of 60° bends and Y-branch power splitters were designed and first efficiently fabricated and characterized. The ARROW structure has a relatively large core size suitable for efficient coupling with a single-mode fiber. Simple capsule-shaped topography defects at 60° photonic crystal (PC) bend corners and Y-branch PC power splitters were used for increasing the broadband light transmission. In the preliminary measurements, the propagation losses of the ARROW PC straight waveguides lower than 2 dB/mm with a long length of 1500 µm were achieved. The average bend loss of 60° PC bend waveguides was lower than 3 dB/bend. For the Y-branch PC power splitters, the average power imbalance was lower than 0.6 dB. The results show that our fabricated Si-based ARROW PCWs with 60° bends and Y-branch structures can provide good light transmission and power-splitting ability.

Embedded biomimetic nanostructures for enhanced optical absorption in thin-film solar cells.

Light-management is critical to thin film solar cells due to their usually limited optical absorption in the active layer. Conventional approaches involve employing separate techniques for anti-reflection and light trapping. Here, we demonstrate an embedded biomimetic nanostructure (EBN) that achieves both effects for hydrogenated amorphous silicon (a-Si:H) solar cells. The fabrication of EBNs is accomplished by patterning an index-matching silicon-nitride layer deposited on a glass substrate using polystyrene nanospheres lithography, followed by reactive ion etching. The profile of EBN is then reproduced layer by layer during the deposition of a-Si:H cells. We show that a solar cell with an optimized EBN exhibits a broadband enhanced external quantum efficiency due to both anti-reflection and light-trapping, with respect to an industrial standard cell using an Asahi U glass substrate which is mostly optimized for light trapping. Overall, the cell with an optimized EBN achieves a large short-circuit current density of 17.74 mA/cm(2), corresponding to a 37.63% enhancement over a flat control cell. The power conversion efficiency is also increased from 5.36% to 8.32%. Moreover, the light management enabled by the EBN remains efficient over a wide range of incident angles up to 60°, which is particularly desirable for real environments with diffused sun light. The novel patterning method is not restricted to a-Si:H solar cells, but is also widely applicable to other thin film materials.

Optical phase modulators using deformable waveguides actuated by micro-electro-mechanical systems.

An optical phase modulator is presented by using micro-electro-mechanical systems to actuate deformable silicon waveguides. Via mechanically stretching the waveguide length, the optical path is extended, resulting in a phase shift. The experimental results show that a phase shift of near 0.4π is achieved at 200 V for both TE- and TM-polarized waves by cascading six phase modulation units, agreeing well with the theoretical prediction. The power consumption is estimated to be smaller than 0.2 mW at 200 V, mainly resulting from the leakage current.

Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits.

We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (Tsub) lower than 400 °C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 µA/µm (n-type) and 297 µA/µm (p-type) @ Vth ± 0.8 V, and higher Ion/Ioff (>105 @|Vd| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to Vth roll-off and S.S. degradation compared to the omega(Ω)-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.

Selection Role of Metal Oxides into Transition Metal Dichalcogenide Monolayers by a Direct Selenization Process.

Direct reduction of metal oxides into a few transition metal dichalcogenide (TMDCs) monolayers has been recently explored as an alternative method for large area and uniform deposition. However, not many studies have addressed the characteristics and requirement of the metal oxides into TMDCs by the selenization/sulfurization processes, yielding a wide range of outstanding properties to poor electrical characteristics with nonuniform films. The large difference implies that the process is yet not fully understood. In particular, the selenization/sulfurization at low temperature leads to poor crystallinity films with poor electrical performance, hindering its practical development. A common approach to improve the quality of the selenized/sulfurized films is by further increasing the process temperature, thus requiring additional transfer in order to explore the electrical properties. Here, we show that by finely tuning the quality of the predeposited oxide the selenization/sulfurization temperature can be largely decreased, avoiding major substrate damage and allowing direct device fabrication. The direct relationship between the role of selecting different metal oxides prepared by e-beam evaporation and reactive sputtering and their oxygen deficiency/vacancy leading to quality influence of TMDCs was investigated in detail. Because of its outstanding physical properties, the formation of tungsten diselenide (WSe2) from the reduction of tungsten oxide (WO x) was chosen as a model for proof of concept. By optimizing the process parameters and the selection of metal oxides, layered WSe2 films with controlled atomic thickness can be demonstrated. Interestingly, the domain size and electrical properties of the layered WSe2 films are highly affected by the quality of the metal oxides, for which the layered WSe2 film with small domains exhibits a metallic behavior and the layered WSe2 films with larger domains provides clear semiconducting behavior. Finally, an 8'' wafer scale-layered WSe2 film was demonstrated, giving a step forward in the development of 2D TMDC electronics in the industry.

Near-infrared femtosecond laser crystallized poly-Si thin film transistors.

Polycrystalline silicon (poly-Si) thin film transistors (TFTs) fabricated by near-infrared femtosecond laser annealing (FLA) are demonstrated. The FLA-annealed poly-Si channels exhibit low tail-state, deep-state, and midgap-state densities of grain traps. Characteristics such as field-effect mobility, threshold voltage, and subthreshold slope for FLA-annealed poly-TFTs are comparable to those of conventional approaches. A wide process window for annealing laser fluences was confirmed by examining the changes in electrical parameters for transistors with various channel dimensions.

Low-Temperature Growth of Hydrogenated Amorphous Silicon Carbide Solar Cell by Inductively Coupled Plasma Deposition Toward High Conversion Efficiency in Indoor Lighting.

A p-a-SiC:H window layer was used in amorphous Si thin film solar cells to boost the conversion efficiency in an indoor lighting of 500 lx. The p-a-SiC:H window layer/p-a-Si:H buffer layer scheme moderates the abrupt band bending across the p/i interface for the enhancement of VOC, JSC and FF in the solar spectra of short wavelengths. The optimized thickness of i-a-Si:H absorber layer is 400 nm to achieve the conversion efficiency of ~9.58% in an AM1.5 G solar spectrum. However, the optimized thickness of the absorber layer can be changed from 400 to 600 nm in the indoor lighting of 500 lx, exhibiting the maximum output power of 25.56 µW/cm2. Furthermore, various durability tests with excellent performance were investigated, which are significantly beneficial to harvest the indoor lights for applications in the self-powered internet of thing (IoT).

High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits.

Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (Ion)/subthreshold swing (S.S.) of 181 µA/µm/107 mV/dec and 188 µA/µm/98 mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390 mV at VDD = 1.0 V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate.

Performance Characterization of Dye-Sensitized Photovoltaics under Indoor Lighting.

Indoor utilization of emerging photovoltaics is promising; however, efficiency characterization under room lighting is challenging. We report the first round-robin interlaboratory study of performance measurement for dye-sensitized photovoltaics (cells and mini-modules) and one silicon solar cell under a fluorescent dim light. Among 15 research groups, the relative deviation in power conversion efficiency (PCE) of the samples reaches an unprecedented 152%. On the basis of the comprehensive results, the gap between photometry and radiometry measurements and the response of devices to the dim illumination are identified as critical obstacles to the correct PCE. Therefore, we use an illuminometer as a prime standard with a spectroradiometer to quantify the intensity of indoor lighting and adopt the reverse-biased current-voltage (I-V) characteristics as an indicator to qualify the I-V sampling time for dye-sensitized photovoltaics. The recommendations can brighten the prospects of emerging photovoltaics for indoor applications.

A facile chemical-mechanical polishing lift-off transfer process toward large scale Cu(In,Ga)Se2 thin-film solar cells on arbitrary substrates.

The fabrication of Cu(In,Ga)Se2 (CIGS) solar cells on flexible substrates is a non-trivial task due to thermal and ion diffusion related issues. In order to circumvent these issues, we have developed a chemical-mechanical polishing lift-off (CMPL) transfer process, enabling the direct transfer of CIGS solar cells from conventional soda-lime glass (SLG) onto arbitrary flexible substrates up to 4 cm(2) in size. The structural and compositional nature of the pre- and post-transferred films is examined using electron microscopy, X-ray diffraction analysis, Raman and photoluminescence spectroscopy. We demonstrate the fabrication of solar cells on a range of flexible substrates while being able to maintain 75% cell efficiency (η) when compared to pre-transferred solar cells. The results obtained in this work suggest that our transfer process offers a highly promising approach toward large scale fabrication of CIGS-based solar cells on a wide variety of flexible substrates, suitable for use in the large scale CIGS photovoltaic industry.

Large-scale micro- and nanopatterns of Cu(In,Ga)Se2 thin film solar cells by mold-assisted chemical-etching process.

A reactive mold-assisted chemical etching (MACE) process through an easy-to-make agarose stamp soaked in bromine methanol etchant to rapidly imprint larger area micro- and nanoarrays on CIGS substrates was demonstrated. Interestingly, by using the agarose stamp during the MACE process with and without additive containing oil and triton, CIGS microdome and microhole arrays can be formed on the CIGS substrate. Detailed formation mechanisms of microstructures and the chemical composition variation after the etching process were investigated. In addition, various microand nanostructures were also demonstrated by this universal approach. The microstructure arrays integrated into standard CIGS solar cells with thinner thickness can still achieve an efficiency of 11.22%, yielding an enhanced efficiency of ∼18% compared with that of their planar counterpart due to an excellent absorption behavior confirmed by the simulation results, which opens up a promising way for the realization of high-efficiency micro- or nanostructured thin-film solar cells. Finally, the complete dissolution of agarose stamp into hot water demonstrates an environmentally friendly method by the mold-assisted chemical etching process through an easy-to-make agarose stamp.

Roll-to-roll fabrication of large scale and regular arrays of three-dimensional nanospikes for high efficiency and flexible photovoltaics.

Three-dimensional (3-D) nanostructures have demonstrated enticing potency to boost performance of photovoltaic devices primarily owning to the improved photon capturing capability. Nevertheless, cost-effective and scalable fabrication of regular 3-D nanostructures with decent robustness and flexibility still remains as a challenging task. Meanwhile, establishing rational design guidelines for 3-D nanostructured solar cells with the balanced electrical and optical performance are of paramount importance and in urgent need. Herein, regular arrays of 3-D nanospikes (NSPs) were fabricated on flexible aluminum foil with a roll-to-roll compatible process. The NSPs have precisely controlled geometry and periodicity which allow systematic investigation on geometry dependent optical and electrical performance of the devices with experiments and modeling. Intriguingly, it has been discovered that the efficiency of an amorphous-Si (a-Si) photovoltaic device fabricated on NSPs can be improved by 43%, as compared to its planar counterpart, in an optimal case. Furthermore, large scale flexible NSP solar cell devices have been fabricated and demonstrated. These results not only have shed light on the design rules of high performance nanostructured solar cells, but also demonstrated a highly practical process to fabricate efficient solar panels with 3-D nanostructures, thus may have immediate impact on thin film photovoltaic industry.