Phase evolution of ultra-thin Ni silicide films on CF4 plasma immersion ion implanted Si.

We present a systematic study on the effects of CF4 plasma immersion ion implantation (PIII) in Si on the phase evolution of ultra-thin Ni silicides. For 3 nm Ni, NiSi2 was formed on Si substrates with and without CF4 PIII at temperature as low as 400 °C. For 6 nm Ni, NiSi was formed on pure Si, while epitaxial NiSi2 was obtained on CF4 PIII Si. The incorporation of C and F atoms in the thin epitaxial NiSi2 significantly reduces the layer resistivity. Increasing the Ni thickness to 8 nm results in the formation of NiSi, where the thermal stability of NiSi, the NiSi/Si interface and Schottky contacts are significantly improved with CF4 PIII. We suggest that the interface energy is lowered by the F and C dopants present in the layer and at the interface, leading to phase evolution of the thin Ni silicide.

Effect of hysteretic and non-hysteretic negative capacitance on tunnel FETs DC performance.

This work experimentally demonstrates that the negative capacitance effect can be used to significantly improve the key figures of merit of tunnel field effect transistor (FET) switches. In the proposed approach, a matching condition is fulfilled between a trained-polycrystalline PZT capacitor and the tunnel FET (TFET) gate capacitance fabricated on a strained silicon-nanowire technology. We report a non-hysteretic switch configuration by combining a homojunction TFET and a negative capacitance effect booster, suitable for logic applications, for which the on-current is increased by a factor of 100, the transconductance by 2 orders of magnitude, and the low swing region is extended. The operation of a hysteretic negative capacitance TFET, when the matching condition for the negative capacitance is fulfilled only in a limited region of operation, is also reported and discussed. In this late case, a limited improvement in the device performance is observed. Overall, the paper demonstrates the main beneficial effects of negative capacitance on TFETs are the overdrive and transconductance amplification, which exactly address the most limiting performances of current TFETs.

Room Temperature Lattice Thermal Conductivity of GeSn Alloys.

CMOS-compatible materials for efficient energy harvesters at temperatures characteristic for on-chip operation and body temperature are the key ingredients for sustainable green computing and ultralow power Internet of Things applications. In this context, the lattice thermal conductivity (κ) of new group IV semiconductors, namely Ge1-xSnx alloys, are investigated. Layers featuring Sn contents up to 14 at.% are epitaxially grown by state-of-the-art chemical-vapor deposition on Ge buffered Si wafers. An abrupt decrease of the lattice thermal conductivity (κ) from 55 W/(m·K) for Ge to 4 W/(m·K) for Ge0.88Sn0.12 alloys is measured electrically by the differential 3ω-method. The thermal conductivity was verified to be independent of the layer thickness for strained relaxed alloys and confirms the Sn dependence observed by optical methods previously. The experimental κ values in conjunction with numerical estimations of the charge transport properties, able to capture the complex physics of this quasi-direct bandgap material system, are used to evaluate the thermoelectric figure of merit ZT for n- and p-type GeSn epitaxial layers. The results highlight the high potential of single-crystal GeSn alloys to achieve similar energy harvest capability as already present in SiGe alloys but in the 20 °C-100 °C temperature range where Si-compatible semiconductors are not available. This opens the possibility of monolithically integrated thermoelectric on the CMOS platform.

Isothermal Heteroepitaxy of Ge1-x Sn x Structures for Electronic and Photonic Applications.

Epitaxy of semiconductor-based quantum well structures is a challenging task since it requires precise control of the deposition at the submonolayer scale. In the case of Ge1-x Sn x alloys, the growth is particularly demanding since the lattice strain and the process temperature greatly impact the composition of the epitaxial layers. In this paper, the realization of high-quality pseudomorphic Ge1-x Sn x layers with Sn content ranging from 6 at. % up to 15 at. % using isothermal processes in an industry-compatible reduced-pressure chemical vapor deposition reactor is presented. The epitaxy of Ge1-x Sn x layers has been optimized for a standard process offering a high Sn concentration at a large process window. By varying the N2 carrier gas flow, isothermal heterostructure designs suitable for quantum transport and spintronic devices are obtained.

Artificial Synapses Based on Ferroelectric Schottky Barrier Field-Effect Transistors for Neuromorphic Applications.

Artificial synapses based on ferroelectric Schottky barrier field-effect transistors (FE-SBFETs) are experimentally demonstrated. The FE-SBFETs employ single-crystalline NiSi2 contacts with an atomically flat interface to Si and Hf0.5Zr0.5O2 ferroelectric layers on silicon-on-insulator substrates. The ferroelectric polarization switching dynamics gradually modulate the NiSi2/Si Schottky barriers and the potential of the channel, thus programming the device conductance with input voltage pulses. The short-term synaptic plasticity is characterized in terms of excitatory/inhibitory post-synaptic current (EPSC) and paired-pulse facilitation/depression. The EPSC amplitude shows a linear response to the amplitude of the pre-synaptic spike. Very low energy/spike consumption as small as ∼2 fJ is achieved, demonstrating high energy efficiency. Long-term potentiation/depression results show very high endurance and very small cycle-to-cycle variations (∼1%) after 105 pulse measurements. Furthermore, spike-timing-dependent plasticity is also emulated using the gate voltage pulse as the pre-synaptic spike and the drain voltage pulse as the post-synaptic spikes. These findings indicate that FE-SBFET synapses have high potential for future neuromorphic computing applications.