A Green High-k Dielectric from Modified Carboxymethyl Cellulose-Based with Dextrin.

Many crucial components inside electronic devices are made from non-renewable, non-biodegradable, and potentially toxic materials, leading to environmental damage. Finding alternative green dielectric materials is mandatory to align with global sustainable goals. Carboxymethyl cellulose (CMC) is a bio-polymer derived from cellulose and has outstanding properties. Herein, citric acid, dextrin, and CMC based hydrogels are prepared, which are biocompatible and biodegradable and exhibit rubber-like mechanical properties, with Young modulus values of 0.89 MPa. Hence, thin film CMC-based hydrogel is explored as a suitable green high-k dielectric candidate for operation at low voltages, demonstrating a high dielectric constant of up to 78. These fabricated transistors reveal stable high capacitance (2090 nF cm-2) for ≈±3 V operation. Using a polyelectrolyte-type approach and poly-(2-vinyl anthracene) (PVAn) surface modification, this study demonstrates a thin dielectric layer (d ≈30 nm) with a small voltage threshold (Vth ≈-0.8 V), moderate transconductance (gm ≈65 nS), and high ON-OFF ratio (≈105). Furthermore, the dielectric layer exhibits stable performance under bias stress of ± 3.5 V and 100 cycles of switching tests. The modified CMC-based hydrogel demonstrates desirable performance as a green dielectric for low-voltage operation, further highlighting its biocompatibility.

2D Indium Phosphorus Sulfide (In2 P3 S9 ): An Emerging van der Waals High-k Dielectrics.

2D van der Waals (vdW) semiconductors hold great potentials for more-than-Moore field-effect transistors (FETs), and the efficient utilization of their theoretical performance requires compatible high-k dielectrics to guarantee the high gate coupling efficiency. The deposition of traditional high-k dielectric oxide films on 2D materials usually generates interface concerns, thereby causing the carrier scattering and degeneration of device performance. Here, utilizing a space-confined epitaxy growth approach, the authors successfully obtained air-stable ultrathin indium phosphorus sulfide (In2 P3 S9 ) nanosheets, the thickness of which can be scaled down to monolayer limit (≈0.69 nm) due to its layered structure. 2D In2 P3 S9 exhibits excellent insulating properties, with a high dielectric constant (≈24) and large breakdown voltage (≈8.1 MV cm-1 ) at room temperature. Serving as gate insulator, ultrathin In2 P3 S9 nanosheet can be integrated into MoS2 FETs with high-quality dielectric/semiconductor interface, thus providing a competitive electrical performance of device with subthreshold swings (SS) down to 88 mV dec-1 and a high ON/OFF ratio of 105 . This study proves an important strategy to prepare 2D vdW high-k dielectrics, and greatly facilitates the ongoing research of 2D materials for functional electronics.

A CMOS-compatible morphotropic phase boundary.

Morphotropic phase boundaries (MPBs) show substantial piezoelectric and dielectric responses, which have practical applications. The predicted existence of MPB in HfO2-ZrO2solid solution thin film has provided a new way to increase the dielectric properties of a silicon-compatible device. Here, we present a new fabrication design by which the density of MPBρMPBand consequently the dielectric constantϵrof HfO2-ZrO2thin film was considerably increased. TheρMPBwas controlled by fabrication of a 10 nm [1 nm Hf0.5Zr0.5O2(ferroelectric)/1 nm ZrO2(antiferroelectric)] nanolaminate followed by an appropriate annealing process. The coexistence of orthorhombic and tetragonal structures, which are the origins of ferroelectric (FE) and antiferroelectric (AFE) behaviors, respectively, was structurally confirmed, and a double hysteresis loop that originates from AFE ordering, with some remnant polarization that originates from FE ordering, was observed inP-Ecurve. A remarkable increase inϵrcompared to the conventional HfO2-ZrO2thin film was achieved by controlling the FE-AFE ratio. The fabrication process was performed at low temperature (250 °C) and the device is compatible with silicon technology, so the new design yields a device that has possible applications in near-future electronics.

Enhanced Deposition Selectivity of High-k Dielectrics by Vapor Dosing and Selective Removal of Phosphonic Acid Inhibitors.

Area-selective atomic layer deposition (AS-ALD), which provides a bottom-up nanofabrication method with atomic-scale precision, has attracted a great deal of attention as a means to alleviate the problems associated with conventional top-down patterning. In this study, we report a methodology for achieving selective deposition of high-k dielectrics by surface modification through vapor-phase functionalization of octadecylphosphonic acid (ODPA) inhibitor molecules accompanied by post-surface treatment. A comparative evaluation of deposition selectivity of ZrO2 thin films deposited with the O2 and O3 reactants was performed on SiO2, TiN, and W substrates, and we confirmed that high enough deposition selectivity over 10 nm can be achieved even after 200 cycles of ALD with the O2 reactant. Subsequently, the electrical properties of ZrO2 films deposited with O2 and O3 reactants were investigated with and without post-deposition treatment. We successfully demonstrated that high-quality ZrO2 thin films with high dielectric constants and stable antiferroelectric properties can be produced by subjecting the films to ozone, which can eliminate carbon impurities within the films. We believe that this work provides a new strategy to achieve highly selective deposition for AS-ALD of dielectric on dielectric (DoD) applications toward upcoming bottom-up nanofabrication.

Organic field-effect transistor memory devices using discrete ferritin nanoparticle-based gate dielectrics.

Organic field-effect transistor (OFET) memory devices made using highly stable iron-storage protein nanoparticle (NP) multilayers and pentacene semiconductor materials are introduced. These transistor memory devices have nonvolatile memory properties that cause reversible shifts in the threshold voltage (Vth ) as a result of charge trapping and detrapping in the protein NP (i.e., the ferritin NP with a ferrihydrite phosphate core) gate dielectric layers rather than the metallic NP layers employed in conventional OFET memory devices. The protein NP-based OFET memory devices exhibit good programmable memory properties, namely, large memory window ΔVth (greater than 20 V), a fast switching speed (10 µs), high ON/OFF current ratio (above 10(4)), and good electrical reliability. The memory performance of the devices is significantly enhanced by molecular-level manipulation of the protein NP layers, and various biomaterials with heme Fe(III) /Fe(II) redox couples similar to a ferrihydrite phosphate core are also employed as charge storage dielectrics. Furthermore, when these protein NP multilayers are deposited onto poly(ethylene naphthalate) substrates coated with an indium tin oxide gate electrode and a 50-nm-thick high-k Al2 O3 gate dielectric layer, the approach is effectively extended to flexible protein transistor memory devices that have good electrical performance within a range of low operating voltages (<10 V) and reliable mechanical bending stability.

Advancements in Complementary Metal-Oxide Semiconductor-Compatible Tunnel Barrier Engineered Charge-Trapping Synaptic Transistors for Bio-Inspired Neural Networks in Harsh Environments.

This study aimed to propose a silicon-on-insulator (SOI)-based charge-trapping synaptic transistor with engineered tunnel barriers using high-k dielectrics for artificial synapse electronics capable of operating at high temperatures. The transistor employed sequential electron trapping and de-trapping in the charge storage medium, facilitating gradual modulation of the silicon channel conductance. The engineered tunnel barrier structure (SiO2/Si3N4/SiO2), coupled with the high-k charge-trapping layer of HfO2 and high-k blocking layer of Al2O3, enabled reliable long-term potentiation/depression behaviors within a short gate stimulus time (100 µs), even under elevated temperatures (75 and 125 °C). Conductance variability was determined by the number of gate stimuli reflected in the maximum excitatory postsynaptic current (EPSC) and the residual EPSC ratio. Moreover, we analyzed the Arrhenius relationship between the EPSC as a function of the gate pulse number (N = 1-100) and the measured temperatures (25, 75, and 125 °C), allowing us to deduce the charge trap activation energy. A learning simulation was performed to assess the pattern recognition capabilities of the neuromorphic computing system using the modified National Institute of Standards and Technology datasheets. This study demonstrates high-reliability silicon channel conductance modulation and proposes in-memory computing capabilities for artificial neural networks using SOI-based charge-trapping synaptic transistors.

Challenges to Optimize Charge Trapping Non-Volatile Flash Memory Cells: A Case Study of HfO2/Al2O3 Nanolaminated Stacks.

The requirements for ever-increasing volumes of data storage have urged intensive studies to find feasible means to satisfy them. In the long run, new device concepts and technologies that overcome the limitations of traditional CMOS-based memory cells will be needed and adopted. In the meantime, there are still innovations within the current CMOS technology, which could be implemented to improve the data storage ability of memory cells-e.g., replacement of the current dominant floating gate non-volatile memory (NVM) by a charge trapping memory. The latter offers better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed and allows vertical stacking. This work provides an overview of our systematic studies of charge-trapping memory cells with a HfO2/Al2O3-based charge-trapping layer prepared by atomic layer deposition (ALD). The possibility to tailor density, energy, and spatial distributions of charge storage traps by the introduction of Al in HfO2 is demonstrated. The impact of the charge trapping layer composition, annealing process, material and thickness of tunneling oxide on the memory windows, and retention and endurance characteristics of the structures are considered. Challenges to optimizing the composition and technology of charge-trapping memory cells toward meeting the requirements for high density of trapped charge and reliable storage with a negligible loss of charges in the CTF memory cell are discussed. We also outline the perspectives and opportunities for further research and innovations enabled by charge-trapping HfO2/Al2O3-based stacks.

Influence of the hBN Dielectric Layers on the Quantum Transport Properties of MoS2 Transistors.

The encapsulation of single-layer 2D materials within hBN has been shown to improve the mobility of these compounds. Nevertheless, the interplay between the semiconductor channel and the surrounding dielectrics is not yet fully understood, especially their electron-phonon interactions. Therefore, here, we present an ab initio study of the coupled electrons and phonon transport properties of MoS2-hBN devices. The characteristics of two transistor configurations are compared to each other: one where hBN is treated as a perfectly insulating, non-vibrating layer and one where it is included in the ab initio domain as MoS2. In both cases, a reduction of the ON-state current by about 50% is observed as compared to the quasi-ballistic limit. Despite the similarity in the current magnitude, explicitly accounting for hBN leads to additional electron-phonon interactions at frequencies corresponding to the breathing mode of the MoS2-hBN system. Moreover, the presence of an hBN layer around the 2D semiconductor affects the Joule-induced temperature distribution within the transistor.

Ultraviolet Light-Densified Oxide-Organic Self-Assembled Dielectrics: Processing Thin-Film Transistors at Room Temperature.

Low-temperature, solution-processable, high-capacitance, and low-leakage gate dielectrics are of great interest for unconventional electronics. Here, we report a near room temperature ultraviolet densification (UVD) methodology for realizing high-performance organic-inorganic zirconia self-assembled nanodielectrics (UVD-ZrSANDs). These UVD-ZrSAND multilayers are grown from solution in ambient, densified by UV radiation, and characterized by X-ray reflectivity, atomic force microscopy, X-ray photoelectron spectroscopy, and capacitance measurements. The resulting UVD-ZrSAND films exhibit large capacitances of >700 nF/cm2 and low leakage current densities of <10-7 A/cm2, which rival or exceed those synthesized by traditional thermal methods. Both the p-type organic semiconductor pentacene and the n-type metal oxide semiconductor In2O3 were used to investigate UVD-ZrSANDs as the gate dielectric in thin-film transistors, affording mobilities of 0.58 and 26.21 cm2/(V s), respectively, at a low gate voltage of 2 V. These results represent a significant advance in fabricating ultra-thin high-performance dielectrics near room temperature and should facilitate their integration into diverse electronic technologies.

Radiation Tolerance and Charge Trapping Enhancement of ALD HfO2/Al2O3 Nanolaminated Dielectrics.

High-k dielectric stacks are regarded as a promising information storage media in the Charge Trapping Non-Volatile Memories, which are the most viable alternative to the standard floating gate memory technology. The implementation of high-k materials in real devices requires (among the other investigations) estimation of their radiation hardness. Here we report the effect of gamma radiation (60Co source, doses of 10 and 10 kGy) on dielectric properties, memory windows, leakage currents and retention characteristics of nanolaminated HfO2/Al2O3 stacks obtained by atomic layer deposition and its relationship with post-deposition annealing in oxygen and nitrogen ambient. The results reveal that depending on the dose, either increase or reduction of all kinds of electrically active defects (i.e., initial oxide charge, fast and slow interface states) can be observed. Radiation generates oxide charges with a different sign in O2 and N2 annealed stacks. The results clearly demonstrate a substantial increase in memory windows of the as-grown and oxygen treated stacks resulting from enhancement of the electron trapping. The leakage currents and the retention times of O2 annealed stacks are not deteriorated by irradiation, hence these stacks have high radiation tolerance.

Engineering Dielectric Materials for High-Performance Organic Light Emitting Transistors (OLETs).

Organic light emitting transistors (OLETs) represent a relatively new technology platform in the field of optoelectronics. An OLET is a device with a two-fold functionality since it behaves as a thin-film transistor and at the same time can generate light under appropriate bias conditions. This Review focuses mainly on one of the building blocks of such device, namely the gate dielectrics, and how it is possible to engineer it to improve device properties and performances. While many findings on gate dielectrics can be easily applied to organic light emitting transistors, we here concentrate on how this layer can be exploited and engineered as an active tool for light manipulation in this novel class of optoelectronic devices.

Atomic force microscopy data of novel high-k hydrocarbon films synthesized on Si wafers for gate dielectric applications.

This article presents data obtained from the atomic force microscopy (AFM) images of ultrathin high-k hydrocarbon (HC) films. The high-k HC films were synthesized on Si(100) wafers at various growth temperatures by using inductively-coupled plasma chemical vapor deposition with CH4 gas and a gas mixture consisting of 10% H2 and 90% Ar. The AFM images were obtained by tapping mode. The AFM results provide the surface topography, roughness, and thickness of the HC films as a function of growth temperature, which are essential data for high-k gate dielectrics of metal-insulator-semiconductor device applications. This data article is related to the article entitled, "Novel high-k gate dielectric properties of ultrathin hydrocarbon films for next-generation metal-insulator-semiconductor devices" (Kim et al., 2020) [1].

Reconfigurable Dipole-Induced Resistive Switching of MoS2 Thin Layers on Nb:SrTiO3.

The controllable band gap and charge-trapping capability of MoS2 render it suitable for use in the fabrication of various electrical devices with high-k dielectric oxides. In this study, we investigated reconfigurable resistance states in a MoS2/Nb:SrTiO3 heterostructure by using conductive atomic force microscopy. Low-resistance and high-resistance states were observed in all MoS2 because of barrier height modification resulting from redistribution of charge and oxygen vacancies in the vicinity of interfaces. In a thin layer of the MoS2 film, the carrier density was high, and layer-dependent transport properties appeared because of the charge separation in MoS2. The hysteresis and switching voltage of the MoS2/Nb:SrTiO3 heterostructure could be varied by controlling the number of layers of MoS2.

Engineering High- k/SiGe Interface with ALD Oxide for Selective GeO x Reduction.

Suppression of electronic defects induced by GeO x at the high- k gate oxide/SiGe interface is critical for implementation of high-mobility SiGe channels in complementary metal-oxide-semiconductor (CMOS) technology. Theoretical and experimental studies have shown that a low defect density interface can be formed with an SiO x-rich interlayer on SiGe. Experimental studies in the literature indicate a better interface formation with Al2O3 in contrast to HfO2 on SiGe; however, the mechanism behind this is not well understood. In this study, the mechanism of forming a low defect density interface between Al2O3/SiGe is investigated using atomic layer deposited (ALD) Al2O3 insertion into or on top of ALD HfO2 gate oxides. To elucidate the mechanism, correlations are made between the defect density determined by impedance measurements and the chemical and physical structures of the interface determined by high-resolution scanning transmission electron microscopy and electron energy loss spectroscopy. The compositional analysis reveals an SiO x rich interlayer for both Al2O3/SiGe and HfO2/SiGe interfaces with the insertion of Al2O3 into or on top of the HfO2 oxide. The data is consistent with the Al2O3 insertion inducing decomposition of the GeO x from the interface to form an electrically passive, SiO x rich interface on SiGe. This mechanism shows that nanolaminate gate oxide chemistry cannot be interpreted as resulting from a simple layer-by-layer ideal ALD process, because the precursor or its reaction products can diffuse through the oxide during growth and react at the semiconductor interface. This result shows that in scaled CMOS, remote oxide ALD (oxide ALD on top of the gate oxide) can be used to suppress electronic defects at gate oxide semiconductor interfaces by oxygen scavenging.

Scalable, High-Performance Printed InO x Transistors Enabled by Ultraviolet-Annealed Printed High- k AlO x Gate Dielectrics.

Inorganic transparent metal oxides represent one of the highest performing material systems for thin-film flexible electronics. Integrating these materials with low-temperature processing and printing technologies could fuel the next generation of ubiquitous transparent devices. In this work, we investigate the integration of UV-annealing with inkjet printing, demonstrating how UV-annealing of high- k AlO x dielectrics facilitates the fabrication of high-performance InO x transistors at low processing temperatures and improves bias-stress stability of devices with all-printed dielectrics, semiconductors, and source/drain electrodes. First, the influence of UV-annealing on printed metal-insulator-metal capacitors is explored, illustrating the effects of UV-annealing on the electrical, chemical, and morphological properties of the printed gate dielectrics. Utilizing these dielectrics, printed InO x transistors were fabricated which achieved exceptional performance at low process temperatures (<250 °C), with linear mobility µlin ≈ 12 ± 1.6 cm2/V s, subthreshold slope <150 mV/dec, Ion/ Ioff > 107, and minimal hysteresis (<50 mV). Importantly, detailed characterization of these UV-annealed printed devices reveals enhanced operational stability, with reduced threshold voltage ( Vt) shifts and more stable on-current. This work highlights a unique, synergistic interaction between low-temperature-processed high- k dielectrics and printed metal oxide semiconductors.

Electronic Structure and Charge-Trapping Characteristics of the Al2O3-TiAlO-SiO2 Gate Stack for Nonvolatile Memory Applications.

In this work, high-k composite TiAlO film has been investigated as charge-trapping material for nonvolatile memory applications. The annealing formed Al2O3-TiAlO-SiO2 dielectric stack demonstrates significant memory effects and excellent reliability properties. The memory device exhibits a large memory window of ~2.6 V under ±8 V sweeping voltage, and it shows only ~14% charge loss after more than 10 years' retention, indicating excellent charge retention properties. The electronic structures of the Al2O3-TiAlO-SiO2 have been studied by X-ray photoelectron spectroscopy measurements, and it reveals that the quantum well and the defect traps in TiAlO film can provide a >1.8 eV deep barrier for charge confinement in the TiAlO layer. The mixing between Al2O3 and TiO2 can increase the defects related to the under-coordinated Ti3+ atoms, thereby enhancing the charge-trapping efficiency of the device. Our work implies that high-k TiAlO composite film is promising for applications in future nonvolatile charge-trapping memories.

Probing Interface Defects in Top-Gated MoS2 Transistors with Impedance Spectroscopy.

The electronic properties of the HfO2/MoS2 interface were investigated using multifrequency capacitance-voltage (C-V) and current-voltage characterization of top-gated MoS2 metal-oxide-semiconductor field effect transistors (MOSFETs). The analysis was performed on few layer (5-10) MoS2 MOSFETs fabricated using photolithographic patterning with 13 and 8 nm HfO2 gate oxide layers formed by atomic layer deposition after in-situ UV-O3 surface functionalization. The impedance response of the HfO2/MoS2 gate stack indicates the existence of specific defects at the interface, which exhibited either a frequency-dependent distortion similar to conventional Si MOSFETs with unpassivated silicon dangling bonds or a frequency dispersion over the entire voltage range corresponding to depletion of the HfO2/MoS2 surface, consistent with interface traps distributed over a range of energy levels. The interface defects density (Dit) was extracted from the C-V responses by the high-low frequency and the multiple-frequency extraction methods, where a Dit peak value of 1.2 × 1013 cm-2 eV-1 was extracted for a device (7-layer MoS2 and 13 nm HfO2) exhibiting a behavior approximating to a single trap response. The MoS2 MOSFET with 4-layer MoS2 and 8 nm HfO2 gave Dit values ranging from 2 × 1011 to 2 × 1013 cm-2 eV-1 across the energy range corresponding to depletion near the HfO2/MoS2 interface. The gate current was below 10-7 A/cm2 across the full bias sweep for both samples indicating continuous HfO2 films resulting from the combined UV ozone and HfO2 deposition process. The results demonstrated that impedance spectroscopy applied to relatively simple top-gated transistor test structures provides an approach to investigate electrically active defects at the HfO2/MoS2 interface and should be applicable to alternative TMD materials, surface treatments, and gate oxides as an interface defect metrology tool in the development of TMD-based MOSFETs.

Transfer-Free Fabrication of Graphene Scaffolds on High-k Dielectrics from Metal-Organic Oligomers.

In situ fabrication of graphene scaffold-ZrO2 nanofilms is achieved by thermal annealing of Zr-based metal-organic oligomers on SiO2 substrates. The structural similarities of the aromatic moieties in the ligand (phenyl-, naphthyl-, anthryl-, and pyrenyl-) compared to graphene play a major role in the ordering of the graphene scaffolds obtained. The depth profiling analysis reveals ultrathin carbon-pure or carbon-rich surfaces of the graphene scaffold-ZrO2 nanofilms. The graphene scaffolds with ∼96.0% transmittance in the visible region and 4.8 nm in thickness can be grown with this non-chemical vapor deposition method. Furthermore, the heterogeneous graphene scaffold-ZrO2 nanofilms show a low sheet resistance of 17.0 kΩ per square, corresponding to electrical conductivity of 3197 S m(-1). The strategy provides a facile method to fabricate graphene scaffolds directly on high-k dielectrics without transferring process, paving the way for its application in fabricating electronic devices.

High-k gate stacks on low bandgap tensile strained Ge and GeSn alloys for field-effect transistors.

We present the epitaxial growth of Ge and Ge0.94Sn0.06 layers with 1.4% and 0.4% tensile strain, respectively, by reduced pressure chemical vapor deposition on relaxed GeSn buffers and the formation of high-k/metal gate stacks thereon. Annealing experiments reveal that process temperatures are limited to 350 °C to avoid Sn diffusion. Particular emphasis is placed on the electrical characterization of various high-k dielectrics, as 5 nm Al2O3, 5 nm HfO2, or 1 nmAl2O3/4 nm HfO2, on strained Ge and strained Ge0.94Sn0.06. Experimental capacitance-voltage characteristics are presented and the effect of the small bandgap, like strong response of minority carriers at applied field, are discussed via simulations.

ZnO-based thin film transistors employing aluminum titanate gate dielectrics deposited by spray pyrolysis at ambient air.

The replacement of SiO2 gate dielectrics with metal oxides of higher dielectric constant has led to the investigation of a wide range of materials with superior properties compared with SiO2. Despite their attractive properties, these high-k dielectrics are usually manufactured using costly vacuum-based techniques. To overcome this bottleneck, research has focused on the development of alternative deposition methods based on solution-processable metal oxides. Here we report the application of spray pyrolysis for the deposition and investigation of Al2x-1·TixOy dielectrics as a function of the [Ti(4+)]/[Ti(4+)+2·Al(3+)] ratio and their implementation in thin film transistors (TFTs) employing spray-coated ZnO as the active semiconducting channels. The films are studied by UV-visible absorption spectroscopy, spectroscopic ellipsometry, impedance spectroscopy, atomic force microscopy, X-ray diffraction and field-effect measurements. Analyses reveal amorphous Al2x-1·TixOy dielectrics that exhibit a wide band gap (∼4.5 eV), low roughness (∼0.9 nm), high dielectric constant (k ∼ 13), Schottky pinning factor S of ∼0.44 and very low leakage currents (<5 nA/cm(2)). TFTs employing stoichiometric Al2O3·TiO2 gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with low operating voltages (∼10 V), negligible hysteresis, high on/off current modulation ratio of ∼10(6), subthreshold swing (SS) of ∼550 mV/dec and electron mobility of ∼10 cm(2) V(-1) s(-1).