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An Analysis of Hole Trapping at Grain Boundary or Poly-Si Floating-Body MOSFET.
Jang, Taejin; Baek, Myung-Hyun; Kim, Hyungjin; Park, Byung-Gook.
Afiliación
  • Jang T; Inter-University Semiconductor Research Center (ISRC) and the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Republic of Korea.
  • Baek MH; Inter-University Semiconductor Research Center (ISRC) and the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Republic of Korea.
  • Kim H; Inter-University Semiconductor Research Center (ISRC) and the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Republic of Korea.
  • Park BG; Inter-University Semiconductor Research Center (ISRC) and the Department of Electrical and Computer Engineering, Seoul National University, Seoul 08826, Republic of Korea.
J Nanosci Nanotechnol ; 18(9): 6584-6587, 2018 09 01.
Article en En | MEDLINE | ID: mdl-29677838

Texto completo: 1 Colección: 01-internacional Banco de datos: MEDLINE Idioma: En Revista: J Nanosci Nanotechnol Año: 2018 Tipo del documento: Article

Texto completo: 1 Colección: 01-internacional Banco de datos: MEDLINE Idioma: En Revista: J Nanosci Nanotechnol Año: 2018 Tipo del documento: Article