Chaotic dynamics in nanoscale NbO2 Mott memristors for analogue computing.

At present, machine learning systems use simplified neuron models that lack the rich nonlinear phenomena observed in biological systems, which display spatio-temporal cooperative dynamics. There is evidence that neurons operate in a regime called the edge of chaos that may be central to complexity, learning efficiency, adaptability and analogue (non-Boolean) computation in brains. Neural networks have exhibited enhanced computational complexity when operated at the edge of chaos, and networks of chaotic elements have been proposed for solving combinatorial or global optimization problems. Thus, a source of controllable chaotic behaviour that can be incorporated into a neural-inspired circuit may be an essential component of future computational systems. Such chaotic elements have been simulated using elaborate transistor circuits that simulate known equations of chaos, but an experimental realization of chaotic dynamics from a single scalable electronic device has been lacking. Here we describe niobium dioxide (NbO2) Mott memristors each less than 100 nanometres across that exhibit both a nonlinear-transport-driven current-controlled negative differential resistance and a Mott-transition-driven temperature-controlled negative differential resistance. Mott materials have a temperature-dependent metal-insulator transition that acts as an electronic switch, which introduces a history-dependent resistance into the device. We incorporate these memristors into a relaxation oscillator and observe a tunable range of periodic and chaotic self-oscillations. We show that the nonlinear current transport coupled with thermal fluctuations at the nanoscale generates chaotic oscillations. Such memristors could be useful in certain types of neural-inspired computation by introducing a pseudo-random signal that prevents global synchronization and could also assist in finding a global minimum during a constrained search. We specifically demonstrate that incorporating such memristors into the hardware of a Hopfield computing network can greatly improve the efficiency and accuracy of converging to a solution for computationally difficult problems.

Memristors with diffusive dynamics as synaptic emulators for neuromorphic computing.

The accumulation and extrusion of Ca2+ in the pre- and postsynaptic compartments play a critical role in initiating plastic changes in biological synapses. To emulate this fundamental process in electronic devices, we developed diffusive Ag-in-oxide memristors with a temporal response during and after stimulation similar to that of the synaptic Ca2+ dynamics. In situ high-resolution transmission electron microscopy and nanoparticle dynamics simulations both demonstrate that Ag atoms disperse under electrical bias and regroup spontaneously under zero bias because of interfacial energy minimization, closely resembling synaptic influx and extrusion of Ca2+, respectively. The diffusive memristor and its dynamics enable a direct emulation of both short- and long-term plasticity of biological synapses, representing an advance in hardware implementation of neuromorphic functionalities.

Repeatable, accurate, and high speed multi-level programming of memristor 1T1R arrays for power efficient analog computing applications.

Beyond use as high density non-volatile memories, memristors have potential as synaptic components of neuromorphic systems. We investigated the suitability of tantalum oxide (TaOx) transistor-memristor (1T1R) arrays for such applications, particularly the ability to accurately, repeatedly, and rapidly reach arbitrary conductance states. Programming is performed by applying an adaptive pulsed algorithm that utilizes the transistor gate voltage to control the SET switching operation and increase programming speed of the 1T1R cells. We show the capability of programming 64 conductance levels with <0.5% average accuracy using 100 ns pulses and studied the trade-offs between programming speed and programming error. The algorithm is also utilized to program 16 conductance levels on a population of cells in the 1T1R array showing robustness to cell-to-cell variability. In general, the proposed algorithm results in approximately 10× improvement in programming speed over standard algorithms that do not use the transistor gate to control memristor switching. In addition, after only two programming pulses (an initialization pulse followed by a programming pulse), the resulting conductance values are within 12% of the target values in all cases. Finally, endurance of more than 10(6) cycles is shown through open-loop (single pulses) programming across multiple conductance levels using the optimized gate voltage of the transistor. These results are relevant for applications that require high speed, accurate, and repeatable programming of the cells such as in neural networks and analog data processing.

Electrical performance and scalability of Pt dispersed SiO2 nanometallic resistance switch.

Highly reproducible bipolar resistance switching was recently demonstrated in a composite material of Pt nanoparticles dispersed in silicon dioxide. Here, we examine the electrical performance and scalability of this system and demonstrate devices with ultrafast (<100 ps) switching, long state retention (no measurable relaxation after 6 months), and high endurance (>3 × 10(7) cycles). A possible switching mechanism based on ion motion in the film is discussed based on these observations.

An analytical approach to engineer multistability in the oscillatory response of a pulse-driven ReRAM.

A nonlinear system, exhibiting a unique asymptotic behaviour, while being continuously subject to a stimulus from a certain class, is said to suffer from fading memory. This interesting phenomenon was first uncovered in a non-volatile tantalum oxide-based memristor from Hewlett Packard Labs back in 2016 out of a deep numerical investigation of a predictive mathematical description, known as the Strachan model, later corroborated by experimental validation. It was then found out that fading memory is ubiquitous in non-volatile resistance switching memories. A nonlinear system may however also exhibit a local form of fading memory, in case, under an excitation from a given family, it may approach one of a number of distinct attractors, depending upon the initial condition. A recent bifurcation study of the Strachan model revealed how, under specific train stimuli, composed of two square pulses of opposite polarity per cycle, the simplest form of local fading memory affects the transient dynamics of the aforementioned Resistive Random Access Memory cell, which, would asymptotically act as a bistable oscillator. In this manuscript we propose an analytical methodology, based on the application of analysis tools from Nonlinear System Theory to the Strachan model, to craft the properties of a generalised pulse train stimulus in such a way to induce the emergence of complex local fading memory effects in the nano-device, which would consequently display an interesting tuneable multistable oscillatory response, around desired resistance states. The last part of the manuscript discusses a case study, shedding light on a potential application of the local history erase effects, induced in the device via pulse train stimulation, for compensating the unwanted yet unavoidable drifts in its resistance state under power off conditions.

High-speed and energy-efficient non-volatile silicon photonic memory based on heterogeneously integrated memresonator.

Recently, interest in programmable photonics integrated circuits has grown as a potential hardware framework for deep neural networks, quantum computing, and field programmable arrays (FPGAs). However, these circuits are constrained by the limited tuning speed and large power consumption of the phase shifters used. In this paper, we introduce the memresonator, a metal-oxide memristor heterogeneously integrated with a microring resonator, as a non-volatile silicon photonic phase shifter. These devices are capable of retention times of 12 hours, switching voltages lower than 5 V, and an endurance of 1000 switching cycles. Also, these memresonators have been switched using 300 ps long voltage pulses with a record low switching energy of 0.15 pJ. Furthermore, these memresonators are fabricated on a heterogeneous III-V-on-Si platform capable of integrating a rich family of active and passive optoelectronic devices directly on-chip to enable in-memory photonic computing and further advance the scalability of integrated photonic processors.

Computing high-degree polynomial gradients in memory.

Specialized function gradient computing hardware could greatly improve the performance of state-of-the-art optimization algorithms. Prior work on such hardware, performed in the context of Ising Machines and related concepts, is limited to quadratic polynomials and not scalable to commonly used higher-order functions. Here, we propose an approach for massively parallel gradient calculations of high-degree polynomials, which is conducive to efficient mixed-signal in-memory computing circuit implementations and whose area scales proportionally with the product of the number of variables and terms in the function and, most importantly, independent of its degree. Two flavors of such an approach are proposed. The first is limited to binary-variable polynomials typical in combinatorial optimization problems, while the second type is broader at the cost of a more complex periphery. To validate the former approach, we experimentally demonstrated solving a small-scale third-order Boolean satisfiability problem based on integrated metal-oxide memristor crossbar circuits, with competitive heuristics algorithm. Simulation results for larger-scale, more practical problems show orders of magnitude improvements in area, speed and energy efficiency compared to the state-of-the-art. We discuss how our work could enable even higher-performance systems after co-designing algorithms to exploit massively parallel gradient computation.

Experimentally validated memristive memory augmented neural network with efficient hashing and similarity search.

Lifelong on-device learning is a key challenge for machine intelligence, and this requires learning from few, often single, samples. Memory-augmented neural networks have been proposed to achieve the goal, but the memory module must be stored in off-chip memory, heavily limiting the practical use. In this work, we experimentally validated that all different structures in the memory-augmented neural network can be implemented in a fully integrated memristive crossbar platform with an accuracy that closely matches digital hardware. The successful demonstration is supported by implementing new functions in crossbars, including the crossbar-based content-addressable memory and locality sensitive hashing exploiting the intrinsic stochasticity of memristor devices. Simulations show that such an implementation can be efficiently scaled up for one-shot learning on more complex tasks. The successful demonstration paves the way for practical on-device lifelong learning and opens possibilities for novel attention-based algorithms that were not possible in conventional hardware.

Measuring the switching dynamics and energy efficiency of tantalum oxide memristors.

We measured the real-time switching of metal-oxide memristors with sub-nanosecond resolution and recorded the evolution of the current and voltage during both ON (set) and OFF (reset) events. From these we determined the dynamical behavior of the conductivity for different applied bias amplitudes. Quantitative analysis of the energy cost and switching dynamics showed 115 fJ for ON-switching and 13 pJ for OFF-switching when resistance change was limited to 200%. Results are presented that show a favorable scaling with speed in terms of energy cost and reducing unnecessary damage to the devices.

Sub-nanosecond switching of a tantalum oxide memristor.

We report sub-nanosecond switching of a metal-oxide-metal memristor utilizing a broadband 20 GHz experimental setup developed to observe fast switching dynamics. Set and reset operations were successfully performed in the tantalum oxide memristor using pulses with durations of 105 and 120 ps, respectively. Reproducibility of the sub-nanosecond switching was also confirmed as the device switched over consecutive cycles.

The switching location of a bipolar memristor: chemical, thermal and structural mapping.

Memristors are memory resistors promising a rapid integration into future memory technologies. However, progress is still critically limited by a lack of understanding of the physical processes occurring at the nanoscale. Here we correlate device electrical characteristics with local atomic structure, chemistry and temperature. We resolved a single conducting channel that is made up of a reduced phase of the as-deposited titanium oxide. Moreover, we observed sufficient Joule heating to induce a crystallization of the oxide surrounding the channel, with a peculiar pattern that finite element simulations correlated with the existence of a hot spot close to the bottom electrode, thus identifying the switching location. This work reports direct observations in all three dimensions of the internal structure of titanium oxide memristors.

Tree-based machine learning performed in-memory with memristive analog CAM.

Tree-based machine learning techniques, such as Decision Trees and Random Forests, are top performers in several domains as they do well with limited training datasets and offer improved interpretability compared to Deep Neural Networks (DNN). However, these models are difficult to optimize for fast inference at scale without accuracy loss in von Neumann architectures due to non-uniform memory access patterns. Recently, we proposed a novel analog content addressable memory (CAM) based on emerging memristor devices for fast look-up table operations. Here, we propose for the first time to use the analog CAM as an in-memory computational primitive to accelerate tree-based model inference. We demonstrate an efficient mapping algorithm leveraging the new analog CAM capabilities such that each root to leaf path of a Decision Tree is programmed into a row. This new in-memory compute concept for enables few-cycle model inference, dramatically increasing 103 × the throughput over conventional approaches.

Analog content-addressable memories with memristors.

A content-addressable memory compares an input search word against all rows of stored words in an array in a highly parallel manner. While supplying a very powerful functionality for many applications in pattern matching and search, it suffers from large area, cost and power consumption, limiting its use. Past improvements have been realized by using memristors to replace the static random-access memory cell in conventional designs, but employ similar schemes based only on binary or ternary states for storage and search. We propose a new analog content-addressable memory concept and circuit to overcome these limitations by utilizing the analog conductance tunability of memristors. Our analog content-addressable memory stores data within the programmable conductance and can take as input either analog or digital search values. Experimental demonstrations, scaled simulations and analysis show that our analog content-addressable memory can reduce area and power consumption, which enables the acceleration of existing applications, but also new computing application areas.

In-Memory Computing with Memristor Content Addressable Memories for Pattern Matching.

The dramatic rise of data-intensive workloads has revived application-specific computational hardware for continuing speed and power improvements, frequently achieved by limiting data movement and implementing "in-memory computation". However, conventional complementary metal oxide semiconductor (CMOS) circuit designs can still suffer low power efficiency, motivating designs leveraging nonvolatile resistive random access memory (ReRAM), and with many studies focusing on crossbar circuit architectures. Another circuit primitive-content addressable memory (CAM)-shows great promise for mapping a diverse range of computational models for in-memory computation, with recent ReRAM-CAM designs proposed but few experimentally demonstrated. Here, programming and control of memristors across an 86 × 12 memristor ternary CAM (TCAM) array integrated with CMOS are demonstrated, and parameter tradeoffs for optimizing speed and search margin are evaluated. In addition to smaller area, this memristor TCAM results in significantly lower power due to very low programmable conductance states, motivating CAM use in a wider range of computational applications than conventional TCAMs are confined to today. Finally, the first experimental demonstration of two computational models in memristor TCAM arrays is reported: regular expression matching in a finite state machine for network security intrusion detection and definable inexact pattern matching in a Levenshtein automata for genomic sequencing.

Structural and chemical characterization of TiO2 memristive devices by spatially-resolved NEXAFS.

We used spatially-resolved NEXAFS (near-edge x-ray absorption fine structure) spectroscopy coupled with microscopy to characterize the electronic, structural and chemical properties of bipolar resistive switching devices. Metal/TiO2/metal devices were electroformed with both bias polarities and then physically opened to study the resulting material changes within the device. Soft x-ray absorption techniques allowed isolated study of the different materials present in the device with 100 nm spatial resolution. The resulting morphology and structural changes reveal a picture of localized polarity-independent heating occurring within these devices initiated by and subsequently accelerating polarity-dependent electrochemical reduction/oxidation processes.

Memristor-Based Analog Computation and Neural Network Classification with a Dot Product Engine.

Using memristor crossbar arrays to accelerate computations is a promising approach to efficiently implement algorithms in deep neural networks. Early demonstrations, however, are limited to simulations or small-scale problems primarily due to materials and device challenges that limit the size of the memristor crossbar arrays that can be reliably programmed to stable and analog values, which is the focus of the current work. High-precision analog tuning and control of memristor cells across a 128 × 64 array is demonstrated, and the resulting vector matrix multiplication (VMM) computing precision is evaluated. Single-layer neural network inference is performed in these arrays, and the performance compared to a digital approach is assessed. Memristor computing system used here reaches a VMM accuracy equivalent of 6 bits, and an 89.9% recognition accuracy is achieved for the 10k MNIST handwritten digit test set. Forecasts show that with integrated (on chip) and scaled memristors, a computational efficiency greater than 100 trillion operations per second per Watt is possible.

Efficient and self-adaptive in-situ learning in multilayer memristor neural networks.

Memristors with tunable resistance states are emerging building blocks of artificial neural networks. However, in situ learning on a large-scale multiple-layer memristor network has yet to be demonstrated because of challenges in device property engineering and circuit integration. Here we monolithically integrate hafnium oxide-based memristors with a foundry-made transistor array into a multiple-layer neural network. We experimentally demonstrate in situ learning capability and achieve competitive classification accuracy on a standard machine learning dataset, which further confirms that the training algorithm allows the network to adapt to hardware imperfections. Our simulation using the experimental parameters suggests that a larger network would further increase the classification accuracy. The memristor neural network is a promising hardware platform for artificial intelligence with high speed-energy efficiency.

Capacitive neural network with neuro-transistors.

Experimental demonstration of resistive neural networks has been the recent focus of hardware implementation of neuromorphic computing. Capacitive neural networks, which call for novel building blocks, provide an alternative physical embodiment of neural networks featuring a lower static power and a better emulation of neural functionalities. Here, we develop neuro-transistors by integrating dynamic pseudo-memcapacitors as the gates of transistors to produce electronic analogs of the soma and axon of a neuron, with "leaky integrate-and-fire" dynamics augmented by a signal gain on the output. Paired with non-volatile pseudo-memcapacitive synapses, a Hebbian-like learning mechanism is implemented in a capacitive switching network, leading to the observed associative learning. A prototypical fully integrated capacitive neural network is built and used to classify inputs of signals.

Spatially uniform resistance switching of low current, high endurance titanium-niobium-oxide memristors.

We analyzed micrometer-scale titanium-niobium-oxide prototype memristors, which exhibited low write-power (<3 µW) and energy (<200 fJ per bit per µm2), low read-power (∼nW), and high endurance (>millions of cycles). To understand their physico-chemical operating mechanisms, we performed in operando synchrotron X-ray transmission nanoscale spectromicroscopy using an ultra-sensitive time-multiplexed technique. We observed only spatially uniform material changes during cell operation, in sharp contrast to the frequently detected formation of a localized conduction channel in transition-metal-oxide memristors. We also associated the response of assigned spectral features distinctly to non-volatile storage (resistance change) and writing of information (application of voltage and Joule heating). These results provide critical insights into high-performance memristors that will aid in device design, scaling and predictive circuit-modeling, all of which are essential for the widespread deployment of successful memristor applications.