Delay characteristics of quasi-nonvolatile memory devices operating in positive feedback mechanism.

This study examines the memory and read delay characteristics of quasi-nonvolatile memory (QNVM) devices operating in a positive feedback mechanism through technology computer-aided design simulation. The QNVM devices exhibit a rapid operation speed of 5 ns, a significant sensing margin of approximately 8.0µA, and a retention time of around 1 s without any external bias. These devices showcase an exceptionally brief read delay of 0.12 ns. The energy band diagrams during the memory operation are analyzed to clarify the factors influencing the read delay. The write and standby conditions modulate the potential barrier height during the standby operation, thereby affecting the read delay. Moreover, the shorter rising time causes the reduction of the read delay. This study demonstrates that the QNVM device has the potential to resolve energy consumption and speed issues in nonvolatile memory devices.

Gate-bias stability of triple-gated feedback field-effect transistors with silicon nanosheet channels.

In this study, we investigate the gate-bias stability of triple-gated feedback field-effect transistors (FBFETs) with Si nanosheet channels. The subthreshold swing (SS) of FBFETs increases from 0.3 mV dec-1to 60 and 80 mV dec-1inp- andn-channel modes, respectively, when a positive bias stress (PBS) is applied for 1000 s. In contrast, the SS value does not change even after a negative bias stress (NBS) is applied for 1000 s. The difference in the switching characteristics under PBS and NBS is attributed to the ability of the interface traps to readily gain electrons from the inversion layer. The switching characteristics deteriorated by PBS are completely recovered after annealing at 300 °C for 10 min, and the characteristics remain stable even after PBS is applied again for 1000 s.

Reconfiguration of operation modes in silicon nanowire field-effect transistors by electrostatic virtual doping.

In this study, we perform reconfigurable n- and p-channel operations of a tri-top-gate field-effect transistor (FET) made of a p+-i-n+silicon nanowire (SiNW). In the reconfigurable FET (RFET), two polarity gates and one control gate induce virtual electrostatic doping in the SiNW channel. The polarity gates are electrically connected to each other and program the channel type, while the control gate modulates the flow of charge carriers in the SiNW channel. The SiNW RFET features simple device design, symmetrical electrical characteristics in the n- and p-channel operation modes using p+-i-n+diode characteristics, and both operation modes exhibit high ON/OFF ratios (∼106) and high ON currents (∼1µAµm-1). The proposed device is demonstrated experimentally using a fully CMOS-compatible top-down processes.

Inverting logic-in-memory cells comprising silicon nanowire feedback field-effect transistors.

In this paper, we propose inverting logic-in-memory (LIM) cells comprising silicon nanowire feedback field-effect transistors with steep switching and holding characteristics. The timing diagrams of the proposed inverting LIM cells under dynamic and static conditions are investigated via mixed-mode technology computer-aided design simulation to verify the performance. The inverting LIM cells have an operating speed of the order of nanoseconds, an ultra-high voltage gain, and a longer retention time than that of conventional dynamic random access memory. The disturbance characteristics of half-selected cells within an inverting LIM array confirm the appropriate functioning of the random access memory array.

Steep switching characteristics of single-gated feedback field-effect transistors.

In this study, we propose newly designed feedback field-effect transistors that utilize the positive feedback of charge carriers in single-gated silicon channels to achieve steep switching behaviors. The band diagram, I-V characteristics, subthreshold swing, and on/off current ratio are analyzed using a commercial device simulator. Our proposed feedback field-effect transistors exhibit subthreshold swings of less than 0.1 mV dec-1, an on/off current ratio of approximately 1011, and an on-current of approximately 10-4 A at room temperature, demonstrating that the switching characteristics are superior to those of other silicon-based devices. In addition, the device parameters that affect the device performance, hysteresis characteristics, and temperature-dependent device characteristics are discussed in detail.

Field-effect modulation of the thermoelectric characteristics of silicon nanowires on plastic substrates.

In this study, we demonstrate the substantial enhancement of the thermoelectric power factors of silicon nanowires (SiNWs) on plastic substrates achievable by field-effect modulation. The Seebeck coefficient and electrical conductivity are adjusted by varying the charge carrier concentration via electrical modulation with a gate voltage in the 0 to ±5 range, thus enhancing the power factors from 2.08 to 935 µW K-2 m-1) for n-type SiNWs, and from 453 to 944 µW K-2 m-1) for p-type SiNWs. The electrically modulated thermoelectric characteristics of SiNWs are analyzed and discussed.

Read Operation Mechanism of Feedback Field-Effect Transistors with Quasi-Nonvolatile Memory States.

In this study, the read operation of feedback field-effect transistors (FBFETs) with quasi-nonvolatile memory states was analyzed using a device simulator. For FBFETs, write pulses of 40 ns formed potential barriers in their channels, and charge carriers were accumulated (depleted) in these channels, generating the memory state "State 1 (State 0)". Read pulses of 40 ns read these states with a retention time of 3 s, and the potential barrier formation and carrier accumulation were influenced by these read pulses. The potential barriers were analyzed, using junction voltage and current density to explore the memory states. Moreover, FBFETs exhibited nondestructive readout characteristics during the read operation, which depended on the read voltage and pulse width.

Binarized neural network of diode array with high concordance to vector-matrix multiplication.

In this study, a binarized neural network (BNN) of silicon diode arrays achieved vector-matrix multiplication (VMM) between the binarized weights and inputs in these arrays. The diodes that operate in a positive-feedback loop in their p+-n-p-n+ device structure possess steep switching and bistable characteristics with an extremely low subthreshold swing (below 1 mV) and a high current ratio (approximately 108). Moreover, the arrays show a self-rectifying functionality and an outstanding linearity by an R-squared value of 0.99986, which allows to compose a synaptic cell with a single diode. A 2 × 2 diode array can perform matrix multiply-accumulate operations for various binarized weight matrix cases with some input vectors, which is in high concordance with the VMM, owing to the high reliability and uniformity of the diodes. Moreover, the disturbance-free, nondestructive readout, and semi-permanent holding characteristics of the diode arrays support the feasibility of implementing the BNN.

Temperature-Dependent Feedback Operations of Triple-Gate Field-Effect Transistors.

In this study, we examine the electrical characteristics of triple-gate feedback field-effect transistors (TG FBFETs) over a temperature range of -200 °C to 280 °C. With increasing temperature from 25 °C to 280 °C, the thermally generated charge carriers increase in the channel regions such that a positive feedback loop forms rapidly. Thus, the latch-up voltage shifts from -1.01 V (1.34 V) to -11.01 V (10.45 V) in the n-channel (p-channel) mode. In contrast, with decreasing temperature from 25 °C to -200 °C, the thermally generated charge carriers decrease, causing a shift in the latch-up voltage in the opposite direction to that of the increasing temperature case. Despite the shift in the latch-up voltage, the TG FBFETs exhibit ideal switching characteristics, with subthreshold swings of 6.6 mV/dec and 7.2 mV/dec for the n-channel and p-channel modes, respectively. Moreover, the memory window widens with increasing temperature. Specifically, at temperatures above 85 °C, the memory windows are wider than 3.05 V and 1.42 V for the n-channel and p-channel modes, respectively.

Generation and Storage of Random Voltage Values via Ring Oscillators Comprising Feedback Field-Effect Transistors.

In this study, we demonstrate the generation and storage of random voltage values using a ring oscillator consisting of feedback field-effect transistors (FBFETs). This innovative approach utilizes the logic-in-memory function of FBFETs to extract continuous output voltages from oscillatory cycles. The ring oscillator exhibited uniform probability distributions of 51.6% for logic 0 and 48.4% for logic 1. The generation of analog voltages provides binary random variables that are stored for over 5000 s. This demonstrates the potential of the ring oscillator in advanced physical functions and true random number generator technologies.

Effect of interface defects on electrical characteristics of a-ITGZO TFTs under bottom, top, and dual gatings.

Here, we investigate the effects of interface defects on the electrical characteristics of amorphous indium-tin-gallium-zinc oxide (a-ITGZO) thin-film transistors (TFTs) utilizing bottom, top, and dual gatings. The field-effect mobility (27.3 cm2/V∙s) and subthreshold swing (222 mV/decade) under a dual gating is substantially better than those under top (12.6 cm2/V∙s, 301 mV/decade) and bottom (11.1 cm2/V∙s, 487 mV/decade) gatings. For an a-ITGZO TFT, oxygen deficiencies are more prevalent in the bottom-gate dielectric interface than in the top-gate dielectric interface, and they are less prevalent inside the channel layer than at the interfaces, indicating that the presence of oxygen deficiencies significantly affects the field-effect mobility and subthreshold swing. Moreover, the variation in the electrical characteristics due to the positive bias stress is discussed here.

Binary and ternary logic-in-memory using nanosheet feedback field-effect transistors with triple-gated structure.

In this study, we demonstrate binary and ternary logic-in-memory (LIM) operations of inverters and NAND and NOR gates comprising nanosheet (NS) feedback field-effect transistors (FBFETs) with a triple-gated structure. The NS FBFETs are reconfigured in p- or n-channel modes depending on the polarity of the gate bias voltage and exhibit steep switching characteristics with an extremely low subthreshold swing of 1.08 mV dec-1 and a high ON/OFF current ratio of approximately 107. Logic circuits consisting of NS FBFETs perform binary and ternary logic operations of the inverters and NAND and NOR gates in each circuit and store their outputs under zero-bias conditions. Therefore, NS FBFETs are promising components for next-generation LIM.

Analysis of thermal degradation of organic light-emitting diodes with infrared imaging and impedance spectroscopy.

We propose a route to examine the thermal degradation of organic light-emitting diodes (OLEDs) with infrared (IR) imaging and impedance spectroscopy. Four different OLEDs with tris (8-hydroxyquinolinato) aluminum are prepared in this study for the analysis of thermal degradation. Our comparison of the thermal and electrical characteristics of these OLEDs reveals that the real-time temperatures of these OLEDs obtained from the IR images clearly correlate with the electrical properties and lifetimes. The OLED with poor electrical properties shows a fairly high temperature during the operation and a considerably short lifetime. Based on the correlation of the real-time temperature and the performance of the OLEDs, the impedance results suggest different thermal degradation mechanisms for each of the OLEDs. The analysis method suggested in this study will be helpful in developing OLEDs with higher efficiency and longer lifetime.

Length-dependent thermoelectric characteristics of silicon nanowires on plastics in a relatively low temperature regime in ambient air.

We report on the thermoelectric characteristics of p-type silicon nanowires (NWs) on plastics in the relatively low temperature regime below 47 °C, and for temperature differences of less than 10 K in ambient air. Thermal profile images are utilized to directly determine the temperature difference in the NWs generated by Joule heating in air. The Seebeck coefficient of the NWs increases from 294 to 414 µV K(-1) as the NW length varies from 40 to 280 µm. For a temperature difference of 7 K, the maximal Seebeck voltage can be estimated to be 2.7 mV for NWs with a length of 280 µm. In contrast, the output power is maximized for NWs length of 240 µm. The maximized output power obtained experimentally in this study is 2.1 pW at a temperature difference of 6 K. The thermoelectric characteristics are analyzed and discussed.

Characterization of planar pn heterojunction diodes constructed with Cu2O nanoparticle films and single ZnO nanowires.

In this study, we fabricate planar pn heterojunction diodes composed of Cu2O nanoparticle (NP) films and single ZnO nanowires (NWs) on SiO2 (300 nm)/Si substrates and investigate their characteristics in the dark and under the illumination of white light and 325 nm wavelength light. The diode at bias voltages of +/- 1 V shows rectification ratios of 10 (in the dark) and 34 (under the illumination of white light). On the other hand, the diode exposed to the 325 nm wavelength light exhibits Ohmic characteristics which are associated with efficient photocurrent generation in both the Cu2O NP film and the single ZnO NW.

Photocurrent characteristics of HgTe nanoparticle films-Si nanowires heterojunctions made using a simple transfer-dropping method.

In this study, pn heterojunction diodes are constructed with p-type HgTe nanoparticle (NP) films dropped by a nanoplotter and n-type Si nanowires (NWs) transferred onto plastic substrates and their optoelectronic characteristics are investigated under the illumination of 633-nm wavelength light. The rectification ratio when light is irradiated on the diode is twice that in the dark. The photocurrent efficiency of the diode at a bias voltage of 2.5 V is determined to be 0.41 microA/W, which is greater than that of the transferred Si NWs.

Nanocrystal-based complementary inverters constructed on flexible plastic substrates.

We demonstrate a nanocrystal (NC)-based complementary inverter constructed on a flexible plastic substrate. The NC-based complementary inverter consists of n-type HgSe NC- and p-type HgTe NC-based thin-film transistors (TFTs). Solid films on a plastic substrate obtained from HgSe and HgTe nanocrystals by thermal transformation are utilized as the n- and p-channel layers in these TFTs, respectively. The electrical properties of these component TFTs on unstrained and strained substrates are characterized and the performance of the inverter on the flexible substrate is investigated. The inverter on the unstrained substrate exhibits a logic gain of about 8, a logic swing of 90%, and a noise margin of 2.0 V. The characteristics of the inverter are changed under tensile and compressive strains, but not very significantly. Moreover, a comparison of the electrical characteristics of the n- and p-channel TFTs and the inverter is made in this paper.

Memory characteristics of doubly stacked nano-floating gate memory devices with channels of single ZnO nanowires.

We present in this paper the memory characteristics of doubly stacked nonvolatile nano-floating gate memory (NFGM) devices with channels of single ZnO nanowires. In our doubly stacked NFGM devices, first- and second-stage floating gate layers composed of Al nanoparticles (NPs) are separated with a 3-nm-thick interlayer of Al2O3. The average size of Al NPs created by sputtering is about 7 nm, and the Al NPs are isolated from each other laterally in the same layer as well as vertically in the double layers. When the voltage is swept from 10 to -10 V, the flat-band voltage shifts are about 0.8 and 2.5 V for the singly and doubly stacked MOS capacitors, respectively. The comparison of metal-oxide-semiconductor capacitors embedded with singly and doubly stacked nanoparticle layers reveals that the retention characteristics of the doubly stacked NFGM device are superior to those of a singly stacked NFGM device. Furthermore, the memory characteristics of the doubly stacked NFGM device remain even after 10(5) programming and erasing cycles.

Influences of electrode materials on the resistive memory switching properties of ZnOxS1-x:Mn thin films.

In this study, we investigate the effect of top electrode (TE) materials on the resistive switching characteristics of TE/ZnOxS1-x:Mn/Al devices. Al, Cu, Au, Ni, and ITO are used as the TE materials of our devices. Except for the ITO TE devices, all the devices show unipolar resistive switching and maintain memory characteristics even after 10(4) s. The ratios of high resistance state (HRS) and low resistance state (LRS) for the Al, Cu, Au, and Ni TE devices are 10(5), 10(5), 10(4), and 10(2), respectively. The low ratio of HRS and LRS of the Ni TE device is attributed to a high magnitude of current at HRS. The Cu/ZnOxS1-x:Mn/Al device shows the smallest distribution of set voltages. The ITO TE device exhibits bipolar resistive switching and suffers change in the resistance at HRS after 10(3) s. Considering the distribution of set voltages and the ratio of HRS and LRS, Cu is the most suitable TE material for the TE/ZnOxS1-x:Mn/Al devices.

Disturbance Characteristics of 1T DRAM Arrays Consisting of Feedback Field-Effect Transistors.

Challenges in scaling dynamic random-access memory (DRAM) have become a crucial problem for implementing high-density and high-performance memory devices. Feedback field-effect transistors (FBFETs) have great potential to overcome the scaling challenges because of their one-transistor (1T) memory behaviors with a capacitorless structure. Although FBFETs have been studied as 1T memory devices, the reliability in an array must be evaluated. Cell reliability is closely related to device malfunction. Hence, in this study, we propose a 1T DRAM consisting of an FBFET with a p+-n-p-n+ silicon nanowire and investigate the memory operation and disturbance in a 3 × 3 array structure through mixed-mode simulations. The 1T DRAM exhibits a write speed of 2.5 ns, a sense margin of 90 µA/µm, and a retention time of approximately 1 s. Moreover, the energy consumption is 5.0 × 10-15 J/bit for the write '1' operation and 0 J/bit for the hold operation. Furthermore, the 1T DRAM shows nondestructive read characteristics, reliable 3 × 3 array operation without any write disturbance, and feasibility in a massive array with an access time of a few nanoseconds.