Monolithic three-dimensional tier-by-tier integration via van der Waals lamination.

Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching1-10. However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics11-13, where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120 °C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers.

Highly Stable HfO2 Memristors through van der Waals Electrode Lamination and Delamination.

Memristors have attracted considerable attention in the past decade, holding great promise for future neuromorphic computing. However, the intrinsic poor stability and large device variability remain key limitations for practical application. Here, we report a simple method to directly visualize the origin of poor stability. By mechanically removing the top electrodes of memristors operated at different states (such as SET or RESET), the memristive layer could be exposed and directly characterized through conductive atomic force microscopy, providing two-dimensional area information within memristors. Based on this technique, we observed the existence of multiple conducting filaments during the formation process and built up a physical model between filament numbers and the cycle-to-cycle variation. Furthermore, by improving the interface quality through the van der Waals top electrode, we could reduce the filament number down to a single filament during all switching cycles, leading to much controlled switching behavior and reliable device operation.

Ag-Assisted Dry Exfoliation of Large-Scale and Continuous 2D Monolayers.

Two-dimensional (2D) semiconductors have generated considerable attention for high-performance electronics and optoelectronics. However, to date, it is still challenging to mechanically exfoliate large-area and continuous monolayers while retaining their intrinsic properties. Here, we report a simple dry exfoliation approach to produce large-scale and continuous 2D monolayers by using a Ag film as the peeling tape. Importantly, the conducting Ag layer could be converted into AgOx nanoparticles at low annealing temperature, directly decoupling the conducting Ag with the underlayer 2D monolayers without involving any solution or etching process. Electrical characterization of the monolayer MoS2 transistor shows a decent carrier mobility of 42 cm2 V-1 s-1 and on-state current of 142 µA/µm. Finally, a plasmonic enhancement photodetector could be simultaneously realized due to the direct formation of Ag nanoparticles arrays on MoS2 monolayers, without complex approaches for nanoparticle synthesis and integration processes, demonstrating photoresponsivity and detectivity of 6.3 × 105 A/W and 2.3 × 1013 Jones, respectively.

High-Density Vertical Transistors with Pitch Size Down to 20 nm.

Vertical field effect transistors (VFETs) have attracted considerable interest for developing ultra-scaled devices. In particular, individual VFET can be stacked on top of another and does not consume additional chip footprint beyond what is needed for a single device at the bottom, representing another dimension for high-density transistors. However, high-density VFETs with small pitch size are difficult to fabricate and is largely limited by the trade-offs between drain thickness and its conductivity. Here, a simple approach is reported to scale the drain to sub-10 nm. By combining 7 nm thick Au with monolayer graphene, the hybrid drain demonstrates metallic behavior with low sheet resistance of ≈100 Ω sq-1 . By van der Waals laminating the hybrid drain on top of 3 nm thick channel and scaling gate stack, the total VFET pitch size down to 20 nm and demonstrates a higher on-state current of 730 A cm-2 . Furthermore, three individual VFETs together are vertically stacked within a vertical distance of 59 nm, representing the record low pitch size for vertical transistors. The method pushes the scaling limit and pitch size limit of VFET, opening up a new pathway for high-density vertical transistors and integrated circuits.

Wafer-scale and universal van der Waals metal semiconductor contact.

Van der Waals (vdW) metallic contacts have been demonstrated as a promising approach to reduce the contact resistance and minimize the Fermi level pinning at the interface of two-dimensional (2D) semiconductors. However, only a limited number of metals can be mechanically peeled and laminated to fabricate vdW contacts, and the required manual transfer process is not scalable. Here, we report a wafer-scale and universal vdW metal integration strategy readily applicable to a wide range of metals and semiconductors. By utilizing a thermally decomposable polymer as the buffer layer, different metals were directly deposited without damaging the underlying 2D semiconductor channels. The polymer buffer could be dry-removed through thermal annealing. With this technique, various metals could be vdW integrated as the contact of 2D transistors, including Ag, Al, Ti, Cr, Ni, Cu, Co, Au, Pd. Finally, we demonstrate that this vdW integration strategy can be extended to bulk semiconductors with reduced Fermi level pinning effect.

Dry Exfoliation of Large-Area 2D Monolayer and Heterostructure Arrays.

Two-dimensional (2D) semiconductors have attracted considerable attention in recent years. However, to date, there is still no effective approach to produce large-scale monolayers while retaining their intrinsic properties. Here, we report a simple mechanical exfoliation method to produce large-scale and high-quality 2D semiconductors, by designing an atomically flat Au-mesh film as the peeling tape. Using our prefabricated mesh tape, the limited contact region (between the 2D crystal and Au) could provide enough adhesion to mechanically exfoliate uniform 2D monolayers, and the noncontact region (between the mesh holes and monolayers) ensures weak interaction to mechanically release the 2D monolayers on desired substrates. Together, we demonstrate a scalable method to dry exfoliate various 2D monolayer arrays onto different substrates without involving any solutions or contaminations, representing the optimization between material yield, scalability, and quality. Furthermore, detailed optical and electrical characterizations are conducted to confirm their intrinsic quality. With the ability to mechanically exfoliate various 2D arrays and further restacking them, we have demonstrated large-scale van der Waals heterostructure arrays through layer-to-layer assembling. Our study offers a simple and scalable method for dry exfoliating 2D monolayer and heterostructure arrays with intrinsic material quality, which could be crucial to accelerate fundamental investigations as well as practical applications of proof-of-concepts devices.