Monolithic three-dimensional tier-by-tier integration via van der Waals lamination.

Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching1-10. However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics11-13, where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120 °C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers.

Edge-by-Edge Lateral Heterostructure through Interfacial Sliding.

van der Waals heterostructures (vdWHs) based on two-dimensional (2D) semiconductors have attracted considerable attention. However, the reported vdWHs are largely based on vertical device structure with large overlapping area, while the realization of lateral heterostructures contacted through 2D edges remains challenging and is majorly limited by the difficulties of manipulating the lateral distance of 2D materials at nanometer scale (during transfer process). Here, we demonstrate a simple interfacial sliding approach for realizing an edge-by-edge lateral contact. By stretching a vertical vdWH, two 2D flakes could gradually slide apart or toward each other. Therefore, by applying proper strain, the initial vertical vdWH could be converted into a lateral heterojunction with intimately contacted 2D edges. The lateral contact structure is supported by both microscope characterization and in situ electrical measurements, exhibiting carrier tunneling behavior. Finally, this approach can be extended to 3D thin films, as demonstrated by the lateral 2D/3D and 3D/3D Schottky junction.

Solid-State Anion Exchange Enabled by Pluggable vdW Assembly for In Situ Halide Manipulation in Perovskite Monocrystalline Film.

The fabrication of perovskite single crystal-based optoelectronics with improved performance is largely hindered by limited processing techniques. Particularly, the local halide composition manipulation, which dominates the bandgap and thus the formation of heterostructures and emission of multiple-wavelength light, is realized via prevalent liquid- or gas-phase anion exchange with the utilization of lithography, while the monocrystalline nature is sacrificed due to polycrystalline transition in exchange with massive defects emerging, impeding carrier separation and transportation. Thus, a damage-free and lithography-free solid-state anion exchange strategy, aiming at in situ halide manipulation in perovskite monocrystalline film, is developed. Typically, CsPbCl3 working as medium to deliver halide is van der Waals (vdW) assembled to specific spots of CsPbBr3, followed by the removal of CsPbCl3 after anion exchange, with the halide composition in contact area modulated and monocrystalline nature of CsPbBr3 preserved. CsPbBr3-CsPbBrxCl3-x monocrystalline heterostructure has been achieved without lithography. Device based on the heterostructure shows apparent rectification behavior and improved photo-response rate. Heterostructure arrays can also be constructed with customized medium crystal. Furthermore, the halide composition can be accurately tuned to enable full coverage of visible spectra. The solid-state exchange enriches the toolbox for processing vulnerable perovskite and paves the way for the integration of monocrystalline perovskite optoelectronics.

Realizing On/Off Ratios over 104 for Sub-2 nm Vertical Transistors.

Vertical transistors hold promise for the development of ultrascaled transistors. However, their on/off ratios are limited by a strong source-drain tunneling current in the off state, particularly for vertical devices with a sub-5 nm channel length. Here, we report an approach for suppressing the off-state tunneling current by designing the barrier height via a van der Waals metal contact. Via lamination of the Pt electrode on a MoS2 vertical transistor, a high Schottky barrier is observed due to their large work function difference, thus suppressing direct tunneling currents. Meanwhile, this "low-energy" lamination process ensures an optimized metal/MoS2 interface with minimized interface states and defects. Together, the highest on/off ratios of 5 × 105 and 104 are realized in vertical transistors with 5 and 2 nm channel lengths, respectively. Our work not only pushes the on/off ratio limit of vertical transistors but also provides a general rule for reducing short-channel effects in ultrascaled devices.

Highly Stable HfO2 Memristors through van der Waals Electrode Lamination and Delamination.

Memristors have attracted considerable attention in the past decade, holding great promise for future neuromorphic computing. However, the intrinsic poor stability and large device variability remain key limitations for practical application. Here, we report a simple method to directly visualize the origin of poor stability. By mechanically removing the top electrodes of memristors operated at different states (such as SET or RESET), the memristive layer could be exposed and directly characterized through conductive atomic force microscopy, providing two-dimensional area information within memristors. Based on this technique, we observed the existence of multiple conducting filaments during the formation process and built up a physical model between filament numbers and the cycle-to-cycle variation. Furthermore, by improving the interface quality through the van der Waals top electrode, we could reduce the filament number down to a single filament during all switching cycles, leading to much controlled switching behavior and reliable device operation.

In Situ Defect Engineering of Controllable Carrier Types in WSe2 for Homomaterial Inverters and Self-Powered Photodetectors.

WSe2 has a high mobility of electrons and holes, which is an ideal choice as active channels of electronics in extensive fields. However, carrier-type tunability of WSe2 still has enormous challenges, which are essential to overcome for practical applications. In this work, the direct growth of n-doped few-layer WSe2 is realized via in situ defect engineering. The n-doping of WSe2 is attributed to Se vacancies induced by the H2 flow purged in the cooling process. The electrical measurements based on field effect transistors demonstrate that the carrier type of WSe2 synthesized is successfully transferred from the conventional p-type to the rarely reported n-type. The electron carrier concentration is efficiently modulated by the concentration of H2 during the cooling process. Furthermore, homomaterial inverters and self-powered photodetectors are fabricated based on the doping-type-tunable WSe2. This work reveals a significant way to realize the controllable carrier type of two-dimensional (2D) materials, exhibiting great potential in future 2D electronics engineering.

Realization of Ultra-Scaled MoS2 Vertical Diodes via Double-Side Electrodes Lamination.

Schottky diode is the fundamental building blocks for modern electronics and optoelectronics. Reducing the semiconductor layer thickness could shrink the vertical size of a Schottky diode, improving its speed and integration density. Here, we demonstrate a new approach to fabricate a Schottky diode with ultrashort physical length approaching atomic limit. By mechanically laminating prefabricated metal electrodes on both-sides of two-dimensional MoS2, the intrinsic metal-semiconductor interfaces can be well retained. As a result, we demonstrate the thinnest Schottky diode with a length of 2.6 nm and decent rectification behavior. Furthermore, with a diode length smaller than the semiconductor depletion length, the carrier transport mechanisms are investigated and explained by thickness-dependent and temperature-dependent electrical measurements. Our study not only pushes the scaling limit of a Schottky diode but also provides a general double-sided electrodes integration approach for other ultrathin vertical devices.

Strain-Plasmonic Coupled Broadband Photodetector Based on Monolayer MoS2.

2D Semiconductors are promising in the development of next-generation photodetectors. However, the performances of 2D photodetectors are largely limited by their poor light absorption (due to ultrathin thickness) and small detection range (due to large bandgap). To overcome the limitations, a strain-plasmonic coupled 2D photodetector is designed by mechanically integrating monolayer MoS2 on top of prefabricated Au nanoparticle arrays. Within this structure, the large biaxial tensile strain can greatly reduce the MoS2 bandgap for broadband photodetection, and at the same time, the nanoparticles can significantly enhance the light intensity around MoS2 with much improved light absorption. Together, the strain-plasmonic coupled photodetector can broaden the detection range by 60 nm and increase the signal-to-noise ratio by 650%, representing the ultimate optimization of detection range and detection intensity at the same time. The strain-plasmonic coupling effect is further systematically characterized and confirmed by using Raman and photoluminescence spectrophotometry. Furthermore, the existence of built-in potential and photo-switching behavior is demonstrated between the strained and unstrained region, constructing a self-powered homojunction photodetector. This approach provides a simple strategy to couple strain effect and plasmonic effect, which can provide a new strategy for designing high-performance and broadband 2D optoelectronic devices.

Ultimate low leakage and EOT of high-κdielectric using transferred metal electrode.

The increase of gate leakage current when the gate dielectric layer is thinned is a key issue for device scalability. For scaling down the integrated circuits, a thin gate dielectric layer with a low leakage current is essential. Currently, changing the dielectric layer material or enhancing the surface contact between the gate dielectric and the channel material is the most common way to reduce gate leakage current in devices. Herein, we report a technique of enhancing the surface contact between the gate dielectric and the metal electrode, that is constructing an Au/Al2O3/Si metal-oxide-semiconductor device by replacing the typical evaporated electrode/dielectric layer contact with a transferred electrode/high-κdielectric layer contact. The contact with a mild, non-invasive interface can ensure the intrinsic insulation of the dielectric layer. By applying 2-40 nm Al2O3as the dielectric layer, the current density-electrical field (J-E) measurement reveals that the dielectric leakage generated by the transferred electrode is less than that obtained by the typical evaporated electrode with a ratio of 0.3 × 101 âˆ¼ 5 × 106atVbias = 1 V. Furthermore, atJ = 1 mA cm-2, the withstand voltage can be raised by 100-102times over that of an evaporated electrode. The capacitance-voltage (C-V) test shows that the transferred metal electrode can efficiently scale the equivalent oxide layer thickness (EOT) to 1.58 nm, which is a relatively smaller value than the overall reported Si-based device's EOT. This finding successfully illustrates that the transferred electrode/dielectric layer's mild contact can balance the scaling of the gate dielectric layer with a minimal leakage current and constantly reduce the EOT. Our enhanced electrode/dielectric contact approach provides a straightforward and effective pathway for further scaling of devices in integrated circuits and significantly decreases the overall integrated circuit's static power consumption (ICs).

Ag-Assisted Dry Exfoliation of Large-Scale and Continuous 2D Monolayers.

Two-dimensional (2D) semiconductors have generated considerable attention for high-performance electronics and optoelectronics. However, to date, it is still challenging to mechanically exfoliate large-area and continuous monolayers while retaining their intrinsic properties. Here, we report a simple dry exfoliation approach to produce large-scale and continuous 2D monolayers by using a Ag film as the peeling tape. Importantly, the conducting Ag layer could be converted into AgOx nanoparticles at low annealing temperature, directly decoupling the conducting Ag with the underlayer 2D monolayers without involving any solution or etching process. Electrical characterization of the monolayer MoS2 transistor shows a decent carrier mobility of 42 cm2 V-1 s-1 and on-state current of 142 µA/µm. Finally, a plasmonic enhancement photodetector could be simultaneously realized due to the direct formation of Ag nanoparticles arrays on MoS2 monolayers, without complex approaches for nanoparticle synthesis and integration processes, demonstrating photoresponsivity and detectivity of 6.3 × 105 A/W and 2.3 × 1013 Jones, respectively.

Ultrashort vertical-channel MoS2 transistor using a self-aligned contact.

Two-dimensional (2D) semiconductors hold great promises for ultra-scaled transistors. In particular, the gate length of MoS2 transistor has been scaled to 1 nm and 0.3 nm using single wall carbon nanotube and graphene, respectively. However, simultaneously scaling the channel length of these short-gate transistor is still challenging, and could be largely attributed to the processing difficulties to precisely align source-drain contact with gate electrode. Here, we report a self-alignment process for realizing ultra-scaled 2D transistors. By mechanically folding a graphene/BN/MoS2 heterostructure, source-drain metals could be precisely aligned around the folded edge, and the channel length is only dictated by heterostructure thickness. Together, we could realize sub-1 nm gate length and sub-50 nm channel length for vertical MoS2 transistor simultaneously. The self-aligned device exhibits on-off ratio over 105 and on-state current of 250 µA/µm at 4 V bias, which is over 40 times higher compared to control sample without self-alignment process.

Mobility Enhancement of Strained MoS2 Transistor on Flat Substrate.

Strain engineering has been proposed as a promising method to boost the carrier mobility of two-dimensional (2D) semiconductors. However, state-of-the-art straining approaches are largely based on putting 2D semiconductors on flexible substrates or rough substrate with nanostructures (e.g., nanoparticles, nanorods, ripples), where the observed mobility change is not only dependent on channel strain but could be impacted by the change of dielectric environment as well as rough interface scattering. Therefore, it remains an open question whether the pure lattice strain could improve the carrier mobilities of 2D semiconductors, limiting the achievement of high-performance 2D transistors. Here, we report a strain engineering approach to fabricate highly strained MoS2 transistors on a flat substrate. By mechanically laminating a prefabricated MoS2 transistor onto a custom-designed trench structure on flat substrate, well-controlled strain can be uniformly generated across the 2D channel. In the meantime, the substrate and the back-gate dielectric layer remain flat without any roughness-induced scattering effect or variation of the dielectric environment. Based on this technique, we demonstrate the MoS2 electron mobility could be enhanced by tension strain and decreased by compression strain, consistent with theoretical predictions. The highest mobility enhancement is 152% for monolayer MoS2 and 64% for bilayer MoS2 transistors, comparable to that of a silicon device. Our method not only provides a compatible approach to uniformly strain the layered semiconductors on flat and solid substrate but also demonstrates an effective method to boost the carrier mobilities of 2D transistors.

High-Density Vertical Transistors with Pitch Size Down to 20 nm.

Vertical field effect transistors (VFETs) have attracted considerable interest for developing ultra-scaled devices. In particular, individual VFET can be stacked on top of another and does not consume additional chip footprint beyond what is needed for a single device at the bottom, representing another dimension for high-density transistors. However, high-density VFETs with small pitch size are difficult to fabricate and is largely limited by the trade-offs between drain thickness and its conductivity. Here, a simple approach is reported to scale the drain to sub-10 nm. By combining 7 nm thick Au with monolayer graphene, the hybrid drain demonstrates metallic behavior with low sheet resistance of ≈100 Ω sq-1 . By van der Waals laminating the hybrid drain on top of 3 nm thick channel and scaling gate stack, the total VFET pitch size down to 20 nm and demonstrates a higher on-state current of 730 A cm-2 . Furthermore, three individual VFETs together are vertically stacked within a vertical distance of 59 nm, representing the record low pitch size for vertical transistors. The method pushes the scaling limit and pitch size limit of VFET, opening up a new pathway for high-density vertical transistors and integrated circuits.

Wafer-scale high-κ dielectrics for two-dimensional circuits via van der Waals integration.

The practical application of two-dimensional (2D) semiconductors for high-performance electronics requires the integration with large-scale and high-quality dielectrics-which however have been challenging to deposit to date, owing to their dangling-bonds-free surface. Here, we report a dry dielectric integration strategy that enables the transfer of wafer-scale and high-κ dielectrics on top of 2D semiconductors. By utilizing an ultra-thin buffer layer, sub-3 nm thin Al2O3 or HfO2 dielectrics could be pre-deposited and then mechanically dry-transferred on top of MoS2 monolayers. The transferred ultra-thin dielectric film could retain wafer-scale flatness and uniformity without any cracks, demonstrating a capacitance up to 2.8 µF/cm2, equivalent oxide thickness down to 1.2 nm, and leakage currents of ~10-7 A/cm2. The fabricated top-gate MoS2 transistors showed intrinsic properties without doping effects, exhibiting on-off ratios of ~107, subthreshold swing down to 68 mV/dec, and lowest interface states of 7.6×109 cm-2 eV-1. We also show that the scalable top-gate arrays can be used to construct functional logic gates. Our study provides a feasible route towards the vdW integration of high-κ dielectric films using an industry-compatible ALD process with well-controlled thickness, uniformity and scalability.

Wafer-scale and universal van der Waals metal semiconductor contact.

Van der Waals (vdW) metallic contacts have been demonstrated as a promising approach to reduce the contact resistance and minimize the Fermi level pinning at the interface of two-dimensional (2D) semiconductors. However, only a limited number of metals can be mechanically peeled and laminated to fabricate vdW contacts, and the required manual transfer process is not scalable. Here, we report a wafer-scale and universal vdW metal integration strategy readily applicable to a wide range of metals and semiconductors. By utilizing a thermally decomposable polymer as the buffer layer, different metals were directly deposited without damaging the underlying 2D semiconductor channels. The polymer buffer could be dry-removed through thermal annealing. With this technique, various metals could be vdW integrated as the contact of 2D transistors, including Ag, Al, Ti, Cr, Ni, Cu, Co, Au, Pd. Finally, we demonstrate that this vdW integration strategy can be extended to bulk semiconductors with reduced Fermi level pinning effect.

Nonlinear co-generation of graphene plasmons for optoelectronic logic operations.

Surface plasmons in graphene provide a compelling strategy for advanced photonic technologies thanks to their tight confinement, fast response and tunability. Recent advances in the field of all-optical generation of graphene's plasmons in planar waveguides offer a promising method for high-speed signal processing in nanoscale integrated optoelectronic devices. Here, we use two counter propagating frequency combs with temporally synchronized pulses to demonstrate deterministic all-optical generation and electrical control of multiple plasmon polaritons, excited via difference frequency generation (DFG). Electrical tuning of a hybrid graphene-fibre device offers a precise control over the DFG phase-matching, leading to tunable responses of the graphene's plasmons at different frequencies across a broadband (0 ~ 50 THz) and provides a powerful tool for high-speed logic operations. Our results offer insights for plasmonics on hybrid photonic devices based on layered materials and pave the way to high-speed integrated optoelectronic computing circuits.

Reconfigurable electronics by disassembling and reassembling van der Waals heterostructures.

Van der Waals heterostructures (vdWHs) have attracted tremendous interest owing to the ability to assemble diverse building blocks without the constraints of lattice matching and processing compatibility. However, once assembled, the fabricated vdWHs can hardly be separated into individual building blocks for further manipulation, mainly due to technical difficulties in the disassembling process. Here, we show a method to disassemble the as-fabricated vdWHs into individual building blocks, which can be further reassembled into new vdWHs with different device functionalities. With this technique, we demonstrate reconfigurable transistors from n-type to p-type and back-gate to dual-gate structures through re-stacking. Furthermore, reconfigurable device behaviors from floating gate memory to Schottky diode and reconfigurable anisotropic Raman behaviors have been obtained through layer re-sequencing and re-twisting, respectively. Our results could lead to a reverse engineering concept of disassembled vdWHs electronics in parallel with state-of-the-art vdWHs electronics, offering a general method for multi-functional pluggable electronics and optoelectronics with limited material building blocks.

Dry Exfoliation of Large-Area 2D Monolayer and Heterostructure Arrays.

Two-dimensional (2D) semiconductors have attracted considerable attention in recent years. However, to date, there is still no effective approach to produce large-scale monolayers while retaining their intrinsic properties. Here, we report a simple mechanical exfoliation method to produce large-scale and high-quality 2D semiconductors, by designing an atomically flat Au-mesh film as the peeling tape. Using our prefabricated mesh tape, the limited contact region (between the 2D crystal and Au) could provide enough adhesion to mechanically exfoliate uniform 2D monolayers, and the noncontact region (between the mesh holes and monolayers) ensures weak interaction to mechanically release the 2D monolayers on desired substrates. Together, we demonstrate a scalable method to dry exfoliate various 2D monolayer arrays onto different substrates without involving any solutions or contaminations, representing the optimization between material yield, scalability, and quality. Furthermore, detailed optical and electrical characterizations are conducted to confirm their intrinsic quality. With the ability to mechanically exfoliate various 2D arrays and further restacking them, we have demonstrated large-scale van der Waals heterostructure arrays through layer-to-layer assembling. Our study offers a simple and scalable method for dry exfoliating 2D monolayer and heterostructure arrays with intrinsic material quality, which could be crucial to accelerate fundamental investigations as well as practical applications of proof-of-concepts devices.

The late parietal event-related potential component is hierarchically sensitive to chunk tightness during chunk decomposition.

The current study analyzed event-related potentials (ERPs) associated with visuo-spatial transformation in order to examine how "chunk tightness" affects the difficulty of chunk decomposition problems. Participants completed a Chinese character decomposition task in three conditions according to the tightness of the to-be-decomposed chunk (tight vs. medium vs. loose). Behavioral data showed that performance became worse (longer reaction time, lower accuracy) as chunk tightness increased. ERP data showed that, as chunk tightness increased, the LPC exhibited a significant decrease at posterior electrode sites. The results indicate that chunk tightness might exert its primary effect on chunk decomposition difficulty by increasing the difficulty of visuo-spatial transformation, a process linked to the parietal LPC.

The Effect of Working Memory Updating Ability on Spatial Insight Problem Solving: Evidence From Behavior and Eye Movement Studies.

It still remains uncertain whether working memory updating ability influences spatial insight problem solving and whether working memory updating ability plays a role in the representation restructuring phase. The current study explored the correlation of working memory updating ability and spatial insight problem solving by behavior and eye movement experiments, and the results showed that high working memory updating ability individuals spend significant shorter time to solve spatial insight problem than low working memory updating ability individuals. For participants with high or low working memory updating ability, the underlying mechanism of spatial insight problem solving is sudden rather than incremental, which demonstrated that the working memory updating ability did not influence the representation restructuring phase. Working memory updating ability influences spatial problem solving, and it works critically in the problem space search phase, while the restructuring phase is sudden and immediate, which is not influenced by working memory updating ability. The representation restructuring tends to be spontaneous.