Monolithic three-dimensional tier-by-tier integration via van der Waals lamination.

Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching1-10. However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics11-13, where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120 °C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers.

van der Waals Contact for Two-Dimensional Transition Metal Dichalcogenides.

Two-dimensional (2D) transition metal dichalcogenides (TMDs) have emerged as highly promising candidates for next-generation electronics owing to their atomically thin structures and surfaces devoid of dangling bonds. However, establishing high-quality metal contacts with TMDs presents a critical challenge, primarily attributed to their ultrathin bodies and delicate lattices. These distinctive characteristics render them susceptible to physical damage and chemical reactions when conventional metallization approaches involving "high-energy" processes are implemented. To tackle this challenge, the concept of van der Waals (vdW) contacts has recently been proposed as a "low-energy" alternative. Within the vdW geometry, metal contacts can be physically laminated or gently deposited onto the 2D channel of TMDs, ensuring the formation of atomically clean and electronically sharp contact interfaces while preserving the inherent properties of the 2D TMDs. Consequently, a considerable number of vdW contact devices have been extensively investigated, revealing unprecedented transport physics or exceptional device performance that was previously unachievable. This review presents recent advancements in vdW contacts for TMD transistors, discussing the merits, limitations, and prospects associated with each device geometry. By doing so, our purpose is to offer a comprehensive understanding of the current research landscape and provide insights into future directions within this rapidly evolving field.

Edge-by-Edge Lateral Heterostructure through Interfacial Sliding.

van der Waals heterostructures (vdWHs) based on two-dimensional (2D) semiconductors have attracted considerable attention. However, the reported vdWHs are largely based on vertical device structure with large overlapping area, while the realization of lateral heterostructures contacted through 2D edges remains challenging and is majorly limited by the difficulties of manipulating the lateral distance of 2D materials at nanometer scale (during transfer process). Here, we demonstrate a simple interfacial sliding approach for realizing an edge-by-edge lateral contact. By stretching a vertical vdWH, two 2D flakes could gradually slide apart or toward each other. Therefore, by applying proper strain, the initial vertical vdWH could be converted into a lateral heterojunction with intimately contacted 2D edges. The lateral contact structure is supported by both microscope characterization and in situ electrical measurements, exhibiting carrier tunneling behavior. Finally, this approach can be extended to 3D thin films, as demonstrated by the lateral 2D/3D and 3D/3D Schottky junction.

Realizing On/Off Ratios over 104 for Sub-2 nm Vertical Transistors.

Vertical transistors hold promise for the development of ultrascaled transistors. However, their on/off ratios are limited by a strong source-drain tunneling current in the off state, particularly for vertical devices with a sub-5 nm channel length. Here, we report an approach for suppressing the off-state tunneling current by designing the barrier height via a van der Waals metal contact. Via lamination of the Pt electrode on a MoS2 vertical transistor, a high Schottky barrier is observed due to their large work function difference, thus suppressing direct tunneling currents. Meanwhile, this "low-energy" lamination process ensures an optimized metal/MoS2 interface with minimized interface states and defects. Together, the highest on/off ratios of 5 × 105 and 104 are realized in vertical transistors with 5 and 2 nm channel lengths, respectively. Our work not only pushes the on/off ratio limit of vertical transistors but also provides a general rule for reducing short-channel effects in ultrascaled devices.

Strain-Plasmonic Coupled Broadband Photodetector Based on Monolayer MoS2.

2D Semiconductors are promising in the development of next-generation photodetectors. However, the performances of 2D photodetectors are largely limited by their poor light absorption (due to ultrathin thickness) and small detection range (due to large bandgap). To overcome the limitations, a strain-plasmonic coupled 2D photodetector is designed by mechanically integrating monolayer MoS2 on top of prefabricated Au nanoparticle arrays. Within this structure, the large biaxial tensile strain can greatly reduce the MoS2 bandgap for broadband photodetection, and at the same time, the nanoparticles can significantly enhance the light intensity around MoS2 with much improved light absorption. Together, the strain-plasmonic coupled photodetector can broaden the detection range by 60 nm and increase the signal-to-noise ratio by 650%, representing the ultimate optimization of detection range and detection intensity at the same time. The strain-plasmonic coupling effect is further systematically characterized and confirmed by using Raman and photoluminescence spectrophotometry. Furthermore, the existence of built-in potential and photo-switching behavior is demonstrated between the strained and unstrained region, constructing a self-powered homojunction photodetector. This approach provides a simple strategy to couple strain effect and plasmonic effect, which can provide a new strategy for designing high-performance and broadband 2D optoelectronic devices.

Transition from Ferromagnetic Semiconductor to Ferromagnetic Metal with Enhanced Curie Temperature in Cr2Ge2Te6 via Organic Ion Intercalation.

Magnetism in the two-dimensional limit has become an intriguing topic for exploring new physical phenomena and potential applications. Especially, the two-dimensional magnetism is often associated with novel intrinsic spin fluctuations and versatile electronic structures, which provides vast opportunities in 2D material research. However, it is still challenging to verify candidate materials hosting two-dimensional magnetism, since the prototype systems have to be realized by using mechanical exfoliation or atomic layer deposition. Here, an alternative manipulation of two-dimensional magnetic properties via electrochemical intercalation of organic molecules is reported. Using tetrabutyl ammonium (TBA+), we synthesized a (TBA)Cr2Ge2Te6 hybrid superlattice with metallic behavior, and the Curie temperature is significantly increased from 67 K in pristine Cr2Ge2Te6 to 208 K in (TBA)Cr2Ge2Te6. Moreover, the magnetic easy axis changes from the ⟨001⟩ direction in Cr2Ge2Te6 to the ab-plane in (TBA)Cr2Ge2Te6. Theoretical calculations indicate that the drastic increase of the Curie temperature can be attributed to the change of magnetic coupling from a weak superexchange interaction in pristine Cr2Ge2Te6 to a strong double-exchange interaction in (TBA)Cr2Ge2Te6. These findings are the first demonstration of manipulation of magnetism in magnetic van der Waals materials by means of intercalating organic ions, which can serve as a convenient and efficient approach to explore versatile magnetic and electronic properties in van der Waals crystals.

Ag-Assisted Dry Exfoliation of Large-Scale and Continuous 2D Monolayers.

Two-dimensional (2D) semiconductors have generated considerable attention for high-performance electronics and optoelectronics. However, to date, it is still challenging to mechanically exfoliate large-area and continuous monolayers while retaining their intrinsic properties. Here, we report a simple dry exfoliation approach to produce large-scale and continuous 2D monolayers by using a Ag film as the peeling tape. Importantly, the conducting Ag layer could be converted into AgOx nanoparticles at low annealing temperature, directly decoupling the conducting Ag with the underlayer 2D monolayers without involving any solution or etching process. Electrical characterization of the monolayer MoS2 transistor shows a decent carrier mobility of 42 cm2 V-1 s-1 and on-state current of 142 µA/µm. Finally, a plasmonic enhancement photodetector could be simultaneously realized due to the direct formation of Ag nanoparticles arrays on MoS2 monolayers, without complex approaches for nanoparticle synthesis and integration processes, demonstrating photoresponsivity and detectivity of 6.3 × 105 A/W and 2.3 × 1013 Jones, respectively.

Ultrashort vertical-channel MoS2 transistor using a self-aligned contact.

Two-dimensional (2D) semiconductors hold great promises for ultra-scaled transistors. In particular, the gate length of MoS2 transistor has been scaled to 1 nm and 0.3 nm using single wall carbon nanotube and graphene, respectively. However, simultaneously scaling the channel length of these short-gate transistor is still challenging, and could be largely attributed to the processing difficulties to precisely align source-drain contact with gate electrode. Here, we report a self-alignment process for realizing ultra-scaled 2D transistors. By mechanically folding a graphene/BN/MoS2 heterostructure, source-drain metals could be precisely aligned around the folded edge, and the channel length is only dictated by heterostructure thickness. Together, we could realize sub-1 nm gate length and sub-50 nm channel length for vertical MoS2 transistor simultaneously. The self-aligned device exhibits on-off ratio over 105 and on-state current of 250 µA/µm at 4 V bias, which is over 40 times higher compared to control sample without self-alignment process.

Mobility Enhancement of Strained MoS2 Transistor on Flat Substrate.

Strain engineering has been proposed as a promising method to boost the carrier mobility of two-dimensional (2D) semiconductors. However, state-of-the-art straining approaches are largely based on putting 2D semiconductors on flexible substrates or rough substrate with nanostructures (e.g., nanoparticles, nanorods, ripples), where the observed mobility change is not only dependent on channel strain but could be impacted by the change of dielectric environment as well as rough interface scattering. Therefore, it remains an open question whether the pure lattice strain could improve the carrier mobilities of 2D semiconductors, limiting the achievement of high-performance 2D transistors. Here, we report a strain engineering approach to fabricate highly strained MoS2 transistors on a flat substrate. By mechanically laminating a prefabricated MoS2 transistor onto a custom-designed trench structure on flat substrate, well-controlled strain can be uniformly generated across the 2D channel. In the meantime, the substrate and the back-gate dielectric layer remain flat without any roughness-induced scattering effect or variation of the dielectric environment. Based on this technique, we demonstrate the MoS2 electron mobility could be enhanced by tension strain and decreased by compression strain, consistent with theoretical predictions. The highest mobility enhancement is 152% for monolayer MoS2 and 64% for bilayer MoS2 transistors, comparable to that of a silicon device. Our method not only provides a compatible approach to uniformly strain the layered semiconductors on flat and solid substrate but also demonstrates an effective method to boost the carrier mobilities of 2D transistors.

High-Density Vertical Transistors with Pitch Size Down to 20 nm.

Vertical field effect transistors (VFETs) have attracted considerable interest for developing ultra-scaled devices. In particular, individual VFET can be stacked on top of another and does not consume additional chip footprint beyond what is needed for a single device at the bottom, representing another dimension for high-density transistors. However, high-density VFETs with small pitch size are difficult to fabricate and is largely limited by the trade-offs between drain thickness and its conductivity. Here, a simple approach is reported to scale the drain to sub-10 nm. By combining 7 nm thick Au with monolayer graphene, the hybrid drain demonstrates metallic behavior with low sheet resistance of ≈100 Ω sq-1 . By van der Waals laminating the hybrid drain on top of 3 nm thick channel and scaling gate stack, the total VFET pitch size down to 20 nm and demonstrates a higher on-state current of 730 A cm-2 . Furthermore, three individual VFETs together are vertically stacked within a vertical distance of 59 nm, representing the record low pitch size for vertical transistors. The method pushes the scaling limit and pitch size limit of VFET, opening up a new pathway for high-density vertical transistors and integrated circuits.

Wafer-scale high-κ dielectrics for two-dimensional circuits via van der Waals integration.

The practical application of two-dimensional (2D) semiconductors for high-performance electronics requires the integration with large-scale and high-quality dielectrics-which however have been challenging to deposit to date, owing to their dangling-bonds-free surface. Here, we report a dry dielectric integration strategy that enables the transfer of wafer-scale and high-κ dielectrics on top of 2D semiconductors. By utilizing an ultra-thin buffer layer, sub-3 nm thin Al2O3 or HfO2 dielectrics could be pre-deposited and then mechanically dry-transferred on top of MoS2 monolayers. The transferred ultra-thin dielectric film could retain wafer-scale flatness and uniformity without any cracks, demonstrating a capacitance up to 2.8 µF/cm2, equivalent oxide thickness down to 1.2 nm, and leakage currents of ~10-7 A/cm2. The fabricated top-gate MoS2 transistors showed intrinsic properties without doping effects, exhibiting on-off ratios of ~107, subthreshold swing down to 68 mV/dec, and lowest interface states of 7.6×109 cm-2 eV-1. We also show that the scalable top-gate arrays can be used to construct functional logic gates. Our study provides a feasible route towards the vdW integration of high-κ dielectric films using an industry-compatible ALD process with well-controlled thickness, uniformity and scalability.

Wafer-scale and universal van der Waals metal semiconductor contact.

Van der Waals (vdW) metallic contacts have been demonstrated as a promising approach to reduce the contact resistance and minimize the Fermi level pinning at the interface of two-dimensional (2D) semiconductors. However, only a limited number of metals can be mechanically peeled and laminated to fabricate vdW contacts, and the required manual transfer process is not scalable. Here, we report a wafer-scale and universal vdW metal integration strategy readily applicable to a wide range of metals and semiconductors. By utilizing a thermally decomposable polymer as the buffer layer, different metals were directly deposited without damaging the underlying 2D semiconductor channels. The polymer buffer could be dry-removed through thermal annealing. With this technique, various metals could be vdW integrated as the contact of 2D transistors, including Ag, Al, Ti, Cr, Ni, Cu, Co, Au, Pd. Finally, we demonstrate that this vdW integration strategy can be extended to bulk semiconductors with reduced Fermi level pinning effect.

Strain Releasing of Flexible 2D Electronics through van der Waals Sliding Contact.

Two-dimensional (2D) materials have demonstrated promising potential for flexible electronics, owning to their atomic thin body thickness and dangling-bond-free surface. Here, we report a sliding contact device structure for efficient strain releasing. By fabricating a weakly coupled metal-2D junction with a van der Waals (vdW) gap in between, the applied strain could be effectively released through their interface sliding; hence minimized strain is transferred to the 2D lattice. Therefore, we observed stable device behavior with electrodes stretching over 110%, much higher than 2D devices using evaporated metal contacts. Furthermore, through multicycle straining-releasing measurements, we found the electrodes still form intimate contact with nearly constant contact resistance during sliding, confirming the optimization of device flexibility and electrical properties at the same time. Finally, we demonstrate this vdW sliding contact is a general device geometry and could be well-extended to various 2D or 3D bulk materials, leading to devices with much higher strain tolerance.

Reversible Superconductor-Insulator Transition in (Li, Fe)OHFeSe Flakes Visualized by Gate-Tunable Scanning Tunneling Spectroscopy.

Electric field control of charge carrier density provides a key in situ technology to continuously tune the ground states and map out the phase diagram of correlated electron systems in one device. This technique is highly expected to be combined with the modern state-of-the art spectroscopic probes, such as angle-resolved photoemission spectroscopy and scanning tunneling microscopy/spectroscopy (STM/S), to efficiently address these states and the underlying physics. However, it is extremely difficult and not successful so far, mainly because the fabrication process of such devices makes them prohibitive for surface probes. Here, by using a solid Li-ion conductor (SIC) as gate dielectric, we have successfully developed gate-tunable STM/S and visualized the superconductor-insulator transition (SIT) in a thin flake of single crystal (Li, Fe)OHFeSe at the nanoscale. The gate-controlled Li-ion injection first enhances the superconductivity and then drives the flake into an inhomogeneous insulating state, where superconductivity is totally suppressed. This process can be reversed by applying an opposite gate voltage. Importantly, the atomically resolved images allow us to identify the critical role that the injected Li ions play in the tuning process. Our results not only provide clear evidence of the microscopic mechanism of the tunable superconductivity and SIT in the SIC-based (Li, Fe)OHFeSe devices, but also establish SIC-gating STM as a powerful tool for investigating the complicated phase diagram of correlated electron system spectroscopically in a single sample with the field-effect approach.

Electric-field-controlled superconductor-ferromagnetic insulator transition.

Superconductivity beyond electron-phonon mechanism is always twisted with magnetism. Based on a new field-effect transistor with solid ion conductor as the gate dielectric (SIC-FET), we successfully achieve an electric-field-controlled phase transition between superconductor and ferromagnetic insulator in (Li,Fe)OHFeSe. A dome-shaped superconducting phase with optimal Tc of 43 K is continuously tuned into a ferromagnetic insulating phase, which exhibits an electric-field-controlled quantum critical behavior. The origin of the ferromagnetism is ascribed to the order of the interstitial Fe ions expelled from the (Li,Fe)OH layers by gating-controlled Li injection. These surprising findings offer a unique platform to study the relationship between superconductivity and ferromagnetism in Fe-based superconductors. This work also demonstrates the superior performance of the SIC-FET in regulating physical properties of layered unconventional superconductors.

Magnetic-field enhanced high-thermoelectric performance in topological Dirac semimetal Cd3As2 crystal.

Thermoelectric materials can be used to convert heat to electric power through the Seebeck effect. We study magneto-thermoelectric figure of merit (ZT) in three-dimensional Dirac semimetal Cd3As2 crystal. It is found that enhancement of power factor and reduction of thermal conductivity can be realized at the same time through magnetic field although magnetoresistivity is greatly increased. ZT can be highly enhanced from 0.17 to 1.1 by more than six times around 350 K under a perpendicular magnetic field of 7 T. The huge enhancement of ZT by magnetic field arises from the linear Dirac band with large Fermi velocity and the large electric thermal conductivity in Cd3As2. Our work paves a new way to greatly enhance the thermoelectric performance in the quantum topological materials.