A Highly Efficient RF-DC Converter for Energy Harvesting Applications Using a Threshold Voltage Cancellation Scheme.

In this paper, a self-threshold voltage (Vth) compensated Radio Frequency to Direct Current (RF-DC) converter operating at 900 MHz and 2.4 GHz is proposed for RF energy harvesting applications. The threshold voltage of the rectifying devices is compensated by the bias voltage generated by the auxiliary transistors and output DC voltage. The auxiliary transistors compensate the threshold voltage (Vth) of the PMOS rectifying device while the threshold voltage (Vth) of the NMOS rectifying device is compensated by the output DC voltage. The proposed RF-DC converter was implemented in 180 nm Complementary Metal-Oxide Semiconductor (CMOS) technology. The experimental results show that the proposed design achieves better performance at both 900 MHz and 2.4 GHz frequencies in terms of PCE, output voltage, sensitivity, and effective area. The peak power conversion efficiency (PCE) of 38.5% at -12 dBm across a 1 MΩ load for 900 MHz frequency was achieved. Similarly, for 2.4 GHz frequency, the proposed circuit achieves a peak PCE of 26.5% at -6 dBm across a 1 MΩ load. The proposed RF-DC converter circuit shows a sensitivity of -20 dBm across a 1 MΩ load and produces a 1 V output DC voltage.

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications.

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.