First realization of the piezoelectronic stress-based transduction device.

We present the first realization of a monolithically integrated piezoelectronic transistor (PET), a new transduction-based computer switch which could potentially operate conventional computer logic at 1/50 the power requirements of current Si-based transistors (Chen 2014 Proc. IEEE ICICDT pp 1-4; Mamaluy et al 2014 Proc. IWCE pp 1-2). In PET operation, an input gate voltage expands a piezoelectric element (PE), transducing the input into a pressure pulse which compresses a piezoresistive element (PR). The PR resistance goes down, transducing the signal back to voltage and turning the switch 'on'. This transduction physics, in principle, allows fast, low-voltage operation. In this work, we address the processing challenges of integrating chemically incompatible PR and PE materials together within a surrounding cage against which the PR can be compressed. This proof-of-concept demonstration of a fully integrated, stand-alone PET device is a key step in the development path toward a fast, low-power very large scale integration technology.

Carbon nanotube complementary wrap-gate transistors.

Among the challenges hindering the integration of carbon nanotube (CNT) transistors in digital technology are the lack of a scalable self-aligned gate and complementary n- and p-type devices. We report CNT transistors with self-aligned gates scaled down to 20 nm in the ideal gate-all-around geometry. Uniformity of the gate wrapping the nanotube channels is confirmed, and the process is shown not to damage the CNTs. Further, both n- and p-type transistors were realized by using the appropriate gate dielectric-HfO2 yielded n-type and Al2O3 yielded p-type-with quantum simulations used to explore the impact of important device parameters on performance. These discoveries not only provide a promising platform for further research into gate-all-around CNT devices but also demonstrate that scalable digital switches with realistic technological potential can be achieved with carbon nanotubes.

Two-dimensional pattern formation using graphoepitaxy of PS-b-PMMA block copolymers for advanced FinFET device and circuit fabrication.

Directed self-assembly (DSA) of lamellar phase block-co-polymers (BCPs) can be used to form nanoscale line-space patterns. However, exploiting the potential of this process for circuit relevant patterning continues to be a major challenge. In this work, we propose a way to impart two-dimensional pattern information in graphoepitaxy-based lamellar phase DSA processes by utilizing the interactions of the BCP with the template pattern. The image formation mechanism is explained through the use of Monte Carlo simulations. Circuit patterns consisting of the active region of Si FinFET transistors, referred to as Si "fins", were fabricated to demonstrate the applicability of this technique to the formation of complex patterns. The quality of the Si fin features produced by this process was validated by demonstrating the first functional DSA-patterned FinFET devices with 29 nm-pitch fins.