Three-Dimensional Integration of InAs Nanowires by Template-Assisted Selective Epitaxy on Tungsten.

3D integration of III-V semiconductors with Si CMOS is highly attractive since it allows combining new functions such as photonic and analog devices with digital signal processing circuitry. Thus far, most 3D integration approaches have used epitaxial growth on Si, layer transfer by wafer bonding, or die-to-die packaging. Here we present low-temperature integration of InAs on W using Si3N4 template assisted selective area metal-organic vapor-phase epitaxy (MOVPE). Despite growth nucleation on polycrystalline W, we can obtain a high yield of single-crystalline InAs nanowires, as observed by transmission electron microscopy (TEM) and electron backscatter diffraction (EBSD). The nanowires exhibit a mobility of 690 cm2/(V s), a low-resistive, Ohmic electrical contact to the W film, and a resistivity which increases with diameter attributed to increased grain boundary scattering. These results demonstrate the feasibility for single-crystalline III-V back-end-of-line integration with a low thermal budget compatible with Si CMOS.

Performance enhancement of GaSb vertical nanowire p-type MOSFETs on Si by rapid thermal annealing.

GaSb is considered as an attractive p-type channel material for future III-V metal-oxide-semiconductor (MOS) technologies, but the processing conditions to utilize the full device potential such as low power logic applications and RF applications still need attention. In this work, applying rapid thermal annealing (RTA) to nanoscale GaSb vertical nanowire p-type MOS field-effect transistors, we have improved the average peak transconductance (gm,peak) by 50% among 28 devices and achieved 70µSµm-1atVDS = -0.5 V in a device with 200 nm gate length. In addition, a low subthreshold swing down to 144 mV dec-1as well as an off-current below 5 nAµm-1which refers to the off-current specification in low-operation-power condition has been obtained. Based on the statistical analysis, the results show a great enhancement in both on- and off-state performance with respect to previous work mainly due to the improved electrostatics and contacts after RTA, leading to a potential in low-power logic applications. We have also examined a short channel device withLg = 80 nm in RTA, which shows an increasedgm,peakup to 149µSµm-1atVDS = -0.5 V as well as a low on-resistance of 4.7 kΩ·µm. The potential of further enhancement ingmvia RTA offers a good alternative to obtain high-performance devices for RF applications which have less stringent requirement for off-state performance. Our results indicate that post-fabrication annealing provides a great option to improve the performance of GaSb-based p-type devices with different structures for various applications.

Feature size control using surface reconstruction temperature in block copolymer lithography for InAs nanowire growth.

Here we present a method to control the size of the openings in hexagonally organized BCP thin films of poly(styrene)-block-poly(4-vinylpyridine) (PS-b-P4VP) by using surface reconstruction. The surface reconstruction is based on selective swelling of the P4VP block in ethanol, and its extraction to the surface of the film, resulting in pores upon drying. We found that the BCP pore diameter increases with ethanol immersion temperature. In our case, the temperature range 18 to 60 °C allowed fine-tuning of the pore size between 14 and 22 nm. A conclusion is that even though the molecular weight of the respective polymer blocks is fixed, the PS-b-P4VP pore diameter can be tuned by controlling temperature during surface reconstruction. These results can be used for BCP-based nanofabrication in general, and for vertical nanowire growth in particular, where high pattern density and diameter control are of importance. Finally, we demonstrate successful growth of indium arsenide InAs vertical nanowires by selective-area metal-organic vapor phase epitaxy (MOVPE), using a silicon nitride mask patterned by the proposed PS-b-P4VP surface reconstruction lithography method.

Impact of source doping on the performance of vertical InAs/InGaAsSb/GaSb nanowire tunneling field-effect transistors.

In this paper, we analyze experimental data from state-of-the-art vertical InAs/InGaAsSb/GaSb nanowire tunneling field-effect transistors (TFETs) to study the influence of source doping on their performance. Overall, the doping level impacts both the off-state and on-state performance of these devices. Separation of the doping from the heterostructure improved the subthreshold swing of the devices. The best devices reached a point subthreshold swing of 30 mV/dec at 100 x higher currents than previous Si-based TFETs. However, separation of doping from the heterostructure had a significant impact on the on-state performance of these devices due to effects related to source depletion. An increase in the doping level helped to improve the on-state performance, which also increased the subthreshold swing. Thus, further optimization of doping incorporation with the heterostructure will help to improve vertical InAs/InGaAsSb/GaSb nanowire TFETs.

Vertical InAs/InGaAs Heterostructure Metal-Oxide-Semiconductor Field-Effect Transistors on Si.

III-V compound semiconductors offer a path to continue Moore's law due to their excellent electron transport properties. One major challenge, integrating III-V's on Si, can be addressed by using vapor-liquid-solid grown vertical nanowires. InAs is an attractive material due to its superior mobility, although InAs metal-oxide-semiconductor field-effect transistors (MOSFETs) typically suffer from band-to-band tunneling caused by its narrow band gap, which increases the off-current and therefore the power consumption. In this work, we present vertical heterostructure InAs/InGaAs nanowire MOSFETs with low off-currents provided by the wider band gap material on the drain side suppressing band-to-band tunneling. We demonstrate vertical III-V MOSFETs achieving off-current below 1 nA/µm while still maintaining on-performance comparable to InAs MOSFETs; therefore, this approach opens a path to address not only high-performance applications but also Internet-of-Things applications that require low off-state current levels.

Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade.

Tunneling field-effect transistors (TunnelFET), a leading steep-slope transistor candidate, is still plagued by defect response, and there is a large discrepancy between measured and simulated device performance. In this work, highly scaled InAs/InxGa1-xAsySb1-y/GaSb vertical nanowire TunnelFET with ability to operate well below 60 mV/decade at technically relevant currents are fabricated and characterized. The structure, composition, and strain is characterized using transmission electron microscopy with emphasis on the heterojunction. Using Technology Computer Aided Design (TCAD) simulations and Random Telegraph Signal (RTS) noise measurements, effects of different type of defects are studied. The study reveals that the bulk defects have the largest impact on the performance of these devices, although for these highly scaled devices interaction with even few oxide defects can have large impact on the performance. Understanding the contribution by individual defects, as outlined in this letter, is essential to verify the fundamental physics of device operation, and thus imperative for taking the III-V TunnelFETs to the next level.

Low Leakage-Current InAsSb Nanowire Photodetectors on Silicon.

Axially doped p-i-n InAs0.93Sb0.07 nanowire arrays have been grown on Si substrates and fabricated into photodetectors for shortwave infrared detection. The devices exhibit a leakage current density around 2 mA/cm(2) and a 20% cutoff of 2.3 µm at 300 K. This record low leakage current density for InAsSb based devices demonstrates the suitability of nanowires for the integration of III-V semiconductors with silicon technology.

III-V Nanowire Complementary Metal-Oxide Semiconductor Transistors Monolithically Integrated on Si.

III-V semiconductors have attractive transport properties suitable for low-power, high-speed complementary metal-oxide-semiconductor (CMOS) implementation, but major challenges related to cointegration of III-V n- and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) on low-cost Si substrates have so far hindered their use for large scale logic circuits. By using a novel approach to grow both InAs and InAs/GaSb vertical nanowires of equal length simultaneously in one single growth step, we here demonstrate n- and p-type III-V MOSFETs monolithically integrated on a Si substrate with high I(on)/I(off) ratios using a dual channel, single gate-stack design processed simultaneously for both types of transistors. In addition, we demonstrate fundamental CMOS logic gates, such as inverters and NAND gates, which illustrate the viability of our approach for large scale III-V MOSFET circuits on Si.

Diameter-Dependent photocurrent in InAsSb nanowire infrared photodetectors.

Photoconductors using vertical arrays of InAs/InAs(1-x)Sb(x) nanowires with varying Sb composition x have been fabricated and characterized. The spectrally resolved photocurrents are strongly diameter dependent with peaks, which are red-shifted with diameter, appearing for thicker wires. Results from numerical simulations are in good agreement with the experimental data and reveal that the peaks are due to resonant modes that enhance the coupling of light into the wires. Through proper selection of wire diameter, the absorptance can be increased by more than 1 order of magnitude at a specific wavelength compared to a thin planar film with the same amount of material. A maximum 20% cutoff wavelength of 5.7 µm is obtained at 5 K for a wire diameter of 717 nm at a Sb content of x = 0.62, but simulations predict that detection at longer wavelengths can be achieved by increasing the diameter. Furthermore, photodetection in InAsSb nanowire arrays integrated on Si substrates is also demonstrated.

Combining axial and radial nanowire heterostructures: radial Esaki diodes and tunnel field-effect transistors.

The ever-growing demand on high-performance electronics has generated transistors with very impressive figures of merit (Radosavljevic et al., IEEE Int. Devices Meeting 2009, 1-4 and Cho et al., IEEE Int. Devices Meeting 2011, 15.1.1-15.1.4). The continued scaling of the supply voltage of field-effect transistors, such as tunnel field-effect transistors (TFETs), requires the implementation of advanced transistor architectures including FinFETs and nanowire devices. Moreover, integration of novel materials with high electron mobilities, such as III-V semiconductors and graphene, are also being considered to further enhance the device properties (del Alamo, Nature 2011, 479, 317-323, and Liao et al., Nature 2010, 467, 305-308). In nanowire devices, boosting the drive current at a fixed supply voltage or maintaining a constant drive current at a reduced supply voltage may be achieved by increasing the cross-sectional area of a device, however at the cost of deteriorated electrostatics. A gate-all-around nanowire device architecture is the most favorable electrostatic configuration to suppress short channel effects; however, the arrangement of arrays of parallel vertical nanowires to address the drive current predicament will require additional chip area. The use of a core-shell nanowire with a radial heterojunction in a transistor architecture provides an attractive means to address the drive current issue without compromising neither chip area nor device electrostatics. In addition to design advantages of a radial transistor architecture, we in this work illustrate the benefit in terms of drive current per unit chip area and compare the experimental data for axial GaSb/InAs Esaki diodes and TFETs to their radial counterparts and normalize the electrical data to the largest cross-sectional area of the nanowire, i.e. the occupied chip area, assuming a vertical device geometry. Our data on lateral devices show that radial Esaki diodes deliver almost 7 times higher peak current, Jpeak = 2310 kA/cm(2), than the maximum peak current of axial GaSb/InAs(Sb) Esaki diodes per unit chip area. The radial TFETs also deliver high peak current densities Jpeak = 1210 kA/cm(2), while their axial counterparts at most carry Jpeak = 77 kA/cm(2), normalized to the largest cross-sectional area of the nanowire.

Single InAs/GaSb nanowire low-power CMOS inverter.

III-V semiconductors have so far predominately been employed for n-type transistors in high-frequency applications. This development is based on the advantageous transport properties and the large variety of heterostructure combinations in the family of III-V semiconductors. In contrast, reports on p-type devices with high hole mobility suitable for complementary metal-oxide-semiconductor (CMOS) circuits for low-power operation are scarce. In addition, the difficulty to integrate both n- and p-type devices on the same substrate without the use of complex buffer layers has hampered the development of III-V based digital logic. Here, inverters fabricated from single n-InAs/p-GaSb heterostructure nanowires are demonstrated in a simple processing scheme. Using undoped segments and aggressively scaled high-κ dielectric, enhancement mode operation suitable for digital logic is obtained for both types of transistors. State-of-the-art on- and off-state characteristics are obtained and the individual long-channel n- and p-type transistors exhibit minimum subthreshold swings of SS = 98 mV/dec and SS = 400 mV/dec, respectively, at V(ds) = 0.5 V. Inverter characteristics display a full signal swing and maximum gain of 10.5 with a small device-to-device variability. Complete inversion is measured at low frequencies although large parasitic capacitances deform the waveform at higher frequencies.

Determination of the bending rigidity of graphene via electrostatic actuation of buckled membranes.

Classical continuum mechanics is used extensively to predict the properties of nanoscale materials such as graphene. The bending rigidity, κ, is an important parameter that is used, for example, to predict the performance of graphene nanoelectromechanical devices and also ripple formation. Despite its importance, there is a large spread in the theoretical predictions of κ for few-layer graphene. We have used the snap-through behavior of convex buckled graphene membranes under the application of electrostatic pressure to determine experimentally values of κ for double-layer graphene membranes. We demonstrate how to prepare convex-buckled suspended graphene ribbons and fully clamped suspended membranes and show how the determination of the curvature of the membranes and the critical snap-through voltage, using AFM, allows us to extract κ. The bending rigidity of bilayer graphene membranes under ambient conditions was determined to be 35.5−15.0 +20.0 eV. Monolayers are shown to have significantly lower κ than bilayers.

Effects of Interface Oxidation on Noise Properties and Performance in III-V Vertical Nanowire Memristors.

Memristors implemented as resistive random-access memories (RRAMs) owing to their low power consumption, scalability, and speed are promising candidates for in-memory computing and neuromorphic applications. Moreover, a vertical 3D implementation of RRAMs enables high-density crossbar arrays at a minimal footprint. Co-integrated III-V vertical gate-all-around MOSFET selectors in a one-transistor-one-resistor (1T1R) configuration have recently been demonstrated where an interlayer (IL)-oxide has been shown to enable high RRAM endurance needed for applications like machine learning. In this work, we evaluate the role of the IL-oxide directly on InAs vertical nanowires using low-frequency noise characterization. We show that the low-frequency noise or the 1/f-noise in InAs vertical RRAMs can be reduced by more than 3 orders of magnitude by engineering the InAs/high-k interface. We also report that the noise properties of the vertical 1T1R do not degrade significantly after RRAM integration making them attractive to be used in emerging electronic circuits.

Carbon nanotube field effect transistors with suspended graphene gates.

Novel field effect transistors with suspended graphene gates are demonstrated. By incorporating mechanical motion of the gate electrode, it is possible to improve the switching characteristics compared to a static gate, as shown by a combination of experimental measurements and numerical simulations. The mechanical motion of the graphene gate is confirmed by using atomic force microscopy to directly measure the electrostatic deflection. The device geometry investigated here can also provide a sensitive measurement technique for detecting high-frequency motion of suspended membranes as required, e.g., for mass sensing.

Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si.

Sb-based semiconductors are critical p-channel materials for III-V complementary metal oxide semiconductor (CMOS) technology, while the performance of Sb-based metal-oxide-semiconductor field-effect transistors (MOSFETs) is typically inhibited by the low quality of the channel to gate dielectric interface, which leads to poor gate modulation. In this study, we achieve improved electrostatics of vertical GaSb nanowire p-channel MOSFETs by employing robust digital etch (DE) schemes, prior to high-κ deposition. Two different processes, based on buffer-oxide etcher (BOE) 30:1 and HCl:IPA 1:10, are compared. We demonstrate that water-based BOE 30:1, which is a common etchant in Si-based CMOS process, gives an equally controllable etching for GaSb nanowires compared to alcohol-based HCl:IPA, thereby realizing III-V on Si with the same etchant selection. Both DE chemicals show good interface quality of GaSb with a substantial reduction in Sb oxides for both etchants while the HCl:IPA resulted in a stronger reduction in the Ga oxides, as determined by X-ray photoelectron spectroscopy and in agreement with the electrical characterization. By implementing these DE schemes into vertical GaSb nanowire MOSFETs, a subthreshold swing of 107 mV/dec is obtained in the HCl:IPA pretreated sample, which is state of the art compared to reported Sb-based MOSFETs, suggesting a potential of Sb-based p-type devices for all-III-V CMOS technologies.

Correction: Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction.

Correction for 'Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction' by Dmitry Dzhigaev et al., Nanoscale, 2020, 12, 14487-14493, DOI: 10.1039/D0NR02260H.

Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performance.

Thin vertical nanowires based on III-V compound semiconductors are viable candidates as channel material in metal oxide semiconductor field effect transistors (MOSFETs) due to attractive carrier transport properties. However, for improved performance in terms of current density as well as contact resistance, adequate characterization techniques for resolving doping distribution within thin vertical nanowires are required. We present a novel method of axially probing the doping profile by systematically changing the gate position, at a constant gate length L g of 50 nm and a channel diameter of 12 nm, along a vertical nanowire MOSFET and utilizing the variations in threshold voltage V T shift (∼100 mV). The method is further validated using the well-established technique of electron holography to verify the presence of the doping profile. Combined, device and material characterizations allow us to in-depth study the origin of the threshold voltage variability typically present for metal organic chemical vapor deposition (MOCVD)-grown III-V nanowire devices.

Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction.

Semiconductor nanowires in wrapped, gate-all-around transistor geometry are highly favorable for future electronics. The advanced nanodevice processing results in strain due to the deposited dielectric and metal layers surrounding the nanowires, significantly affecting their performance. Therefore, non-destructive nanoscale characterization of complete devices is of utmost importance due to the small feature sizes and three-dimensional buried structure. Direct strain mapping inside heterostructured GaSb-InAs nanowire tunnel field-effect transistor embedded in dielectric HfO2, W metal gate layers, and an organic spacer is performed using fast scanning X-ray nanodiffraction. The effect of 10 nm W gate on a single embedded nanowire with segment diameters down to 40 nm is retrieved. The tensile strain values reach 0.26% in the p-type GaSb segment of the transistor. Supported by the finite element method simulation, we establish a connection between the Ar pressure used during the W layer deposition and the nanowire strain state. Thus, we can benchmark our models for further improvements in device engineering. Our study indicates, how the significant increase in X-ray brightness at 4th generation synchrotron, makes high-throughput measurements on realistic nanoelectronic devices viable.

The dependence of the Schottky barrier height on carbon nanotube diameter for Pd-carbon nanotube contacts.

Direct measurements are presented of the Schottky barrier (SB) heights of carbon nanotube devices contacted with Pd electrodes. The SB barrier heights were determined from the activation energy of the temperature-dependent thermionic emission current in the off-state of the devices. The barrier heights generally decrease with increasing diameter of the nanotubes and they are in agreement with the values expected when assuming little or no influence of Fermi level pinning.

Fabrication of crossed junctions of semiconducting and metallic carbon nanotubes: a CNT-gated CNT-FET.

We have developed a method to fabricate crossed junctions between semiconducting (s) and metallic (m) carbon nanotubes (CNTs) combining electric field directed chemical vapor deposition growth and dielectrophoretic alignment. By separating the s- and m-CNTs with a thin dielectric an ultra-small field effect transistor (FET) was fabricated. By using the m-CNT as a gate it was possible to modulate the source-drain current through the s-CNT FET channel. We have also used the m-CNT as an electrical lead. An off-state current lowering was observed when the m-CNT lead was used as a drain electrode.