Tuning of Schottky Barrier Height at NiSi/Si Contact by Combining Dual Implantation of Boron and Aluminum and Microwave Annealing.

Dopant-segregated source/drain contacts in a p-channel Schottky-barrier metal-oxide semiconductor field-effect transistor (SB-MOSFET) require further hole Schottky barrier height (SBH) regulation toward sub-0.1 eV levels to improve their competitiveness with conventional field-effect transistors. Because of the solubility limits of dopants in silicon, the requirements for effective hole SBH reduction with dopant segregation cannot be satisfied using mono-implantation. In this study, we demonstrate a potential solution for further SBH tuning by implementing the dual implantation of boron (B) and aluminum (Al) in combination with microwave annealing (MWA). By using such a method, not only has the lowest hole SBH ever with 0.07 eV in NiSi/n-Si contacts been realized, but also the annealing duration of MWA was sharply reduced to 60 s. Moreover, we investigated the SBH tuning mechanisms of the dual-implanted diodes with microwave annealing, including the dopant segregation, activation effect, and dual-barrier tuning effect of Al. With the selection of appropriate implantation conditions, the dual implantation of B and Al combined with the MWA technique shows promise for the fabrication of future p-channel SB-MOSFETs with a lower thermal budget.

Schottky Barrier Height Tuning via the Dopant Segregation Technique through Low-Temperature Microwave Annealing.

The Schottky junction source/drain structure has great potential to replace the traditional p/n junction source/drain structure of the future ultra-scaled metal-oxide-semiconductor field effect transistors (MOSFETs), as it can form ultimately shallow junctions. However, the effective Schottky barrier height (SBH) of the Schottky junction needs to be tuned to be lower than 100 meV in order to obtain a high driving current. In this paper, microwave annealing is employed to modify the effective SBH of NiSi on Si via boron or arsenic dopant segregation. The barrier height decreased from 0.4-0.7 eV to 0.2-0.1 eV for both conduction polarities by annealing below 400 °C. Compared with the required temperature in traditional rapid thermal annealing, the temperature demanded in microwave annealing is ~60 °C lower, and the mechanisms of this observation are briefly discussed. Microwave annealing is hence of high interest to future semiconductor processing owing to its unique capability of forming the metal/semiconductor contact at a remarkably lower temperature.