Low-loss silicon nitride photonic ICs for near-infrared wavelength bandwidth.

Low-loss photonic integrated circuits (PICs) are the key elements in future quantum technologies, nonlinear photonics and neural networks. The low-loss photonic circuits technology targeting C-band application is well established across multi-project wafer (MPW) fabs, whereas near-infrared (NIR) PICs suitable for the state-of-the-art single-photon sources are still underdeveloped. Here, we report the labs-scale process optimization and optical characterization of low-loss tunable photonic integrated circuits for single-photon applications. We demonstrate the lowest propagation losses to the date (as low as 0.55 dB/cm at 925 nm wavelength) in single-mode silicon nitride submicron waveguides (220×550 nm). This performance is achieved due to advanced e-beam lithography and inductively coupled plasma reactive ion etching steps which yields waveguides vertical sidewalls with down to 0.85 nm sidewall roughness. These results provide a chip-scale low-loss PIC platform that could be even further improved with high quality SiO2 cladding, chemical-mechanical polishing and multistep annealing for extra-strict single-photon applications.

Integrated membrane-free thermal flow sensor for silicon-on-glass microfluidics.

Lab-on-a-chip (LOC) forms the basis of new-generation portable analytical systems. LOC allows the manipulation of ultralow flows of liquid reagents and multistep reactions on a microfluidic chip, which requires a robust and precise instrument to control the flow of liquids on a chip. However, commercially available flow meters appear to be a standalone option adding a significant dead volume of tubes for connection to the chip. Furthermore, most of them cannot be fabricated within the same technological cycle as microfluidic channels. Here, we report on a membrane-free microfluidic thermal flow sensor (MTFS) that can be integrated into a silicon-glass microfluidic chip with a microchannel topology. We propose a membrane-free design with thin-film thermo-resistive sensitive elements isolated from microfluidic channels and a 4'' wafer silicon-glass fabrication route. It ensures MTFS compatibility with corrosive liquids, which is critically important for biological applications. MTFS design rules for the best sensitivity and measurement range are proposed. A method for automated thermo-resistive sensitive element calibration is described. The device parameters are experimentally tested for hundreds of hours with a reference Coriolis flow sensor demonstrating a relative flow error of less than 5% within the range of 2-30 µL min-1 along with a sub-second time response.

Self-Controlled Cleaving Method for Silicon DRIE Process Cross-Section Characterization.

Advanced microsystems widely used in integrated optoelectronic devices, energy harvesting components, and microfluidic lab-on-chips require high-aspect silicon microstructures with a precisely controlled profile. Such microstructures can be fabricated using the Bosch process, which is a key process for the mass production of micro-electro-mechanical systems (MEMS) devices. One can measure the etching profile at a cross-section to characterize the Bosch process quality by cleaving the substrate into two pieces. However, the cleaving process of several neighboring deeply etched microstructures is a very challenging and uncontrollable task. The cleaving method affects both the cleaving efficiency and the metrology quality of the resulting etched microstructures. The standard cleaving technique using a diamond scriber does not solve this issue. Herein, we suggest a highly controllable cross-section cleaving method, which minimizes the effect on the resulting deep etching profile. We experimentally compare two cleaving methods based on various auxiliary microstructures: (1) etched transverse auxiliary lines of various widths (from 5 to 100 µm) and positions; and (2) etched dashed auxiliary lines. The interplay between the auxiliary lines and the etching process is analyzed for dense periodic and isolated trenches sized from 2 to 50 µm with an aspect ratio of more than 10. We experimentally showed that an incorrect choice of auxiliary line parameters leads to silicon "build-up" defects at target microstructures intersections, which significantly affects the cross-section profile metrology. Finally, we suggest a highly controllable defect-free cross-section cleaving method utilizing dashed auxiliary lines with the stress concentrators.