Key material parameters driving CBRAM device performances.

This study is focused on Conductive Bridging Random Access Memory (CBRAM) devices based on chalcogenide electrolyte and Cu-supply materials, and aims at identifying the key material parameters controlling memory properties. The CBRAM devices investigated are integrated on CMOS select transistors, and are constituted by either Ge-Se or Ge-Te electrolyte layers of various compositions combined with a Cu2GeTe3 active chalcogenide electrode. By means of extensive physical and electrical characterization, we show for a given electrolyte system that slower write is obtained for a denser electrolyte layer, which is directly correlated with a lower atomic percentage of the chalcogen element in the layer. We also evidence that the use of Ge-Se electrolyte results in larger write energy (voltage and time), however with improved state retention properties than for Ge-Te electrolyte materials. We associate these results with the stronger chemical bonding of Cu with Se, resulting both in a stabilized Cu filament and a slower Cu cation motion. More robust processing thermal stability is also observed for Ge-Se compared to Ge-Te compounds, allowing more flexibility in the integration flow design.

Three-dimensional observation of the conductive filament in nanoscaled resistive memory devices.

The basic unit of information in filamentary-based resistive switching memories is physically stored in a conductive filament. Therefore, the overall performance of the device is indissolubly related to the properties of such filament. In this Letter, we report for the first time on the three-dimensional (3D) observation of the shape of the conductive filament. The observation of the filament is done in a nanoscale conductive-bridging device, which is programmed under real operative conditions. To obtain the 3D-information we developed a dedicated tomography technique based on conductive atomic force microscopy. The shape and size of the conductive filament are obtained in three-dimensions with nanometric resolution. The observed filament presents a conical shape with the narrow part close to the inert-electrode. On the basis of this shape, we conclude that the dynamic filament-growth is limited by the cation transport. In addition, we demonstrate the role of the programming current, which clearly influences the physical-volume of the induced conductive filaments.

Improvement of the Ferroelectric Response of La-Doped Hafnium Zirconium Oxide Employing Tungsten Oxide Interfacial Layer with Back-End-of-Line Compatibility.

In this work, the impact of a tungsten oxide (WO3) seed and capping layer for ferroelectric La-doped (Hf, Zr)O2 (La:HZO) based capacitors, designed with back-end-of-line (BEOL) compatibility, is systematically investigated. The WO3 capping layer supplies oxygen to the La:HZO layer throughout the fabrication process and during device cycling. This facilitates the annihilation of oxygen vacancies (Vo) within the La:HZO layer, thereby stabilizing its ferroelectric orthorhombic phase and resulting in an increase of the remanent polarization (Pr) value in the capacitor. Moreover, the effectiveness of the WO3 capping layer depends on the seed layer of the HZO film, suggesting that proper combination of the seed and capping layers should be employed to maximize the ferroelectric response. Finally, a TiN/TiO2 seed layer/La:HZO/WO3 capping layer/TiN capacitor is successfully fabricated and optimized by a complete set of atomic layer deposition (ALD) processes, achieving a superior 2Pr value and endurance value of more than 109 cycles at an electric field of 2.5 MV/cm. The WO3 capping layer is anticipated to offer a viable solution for doped HZO capacitors with reduced thickness, addressing the challenge of elevated Vo levels that favor the tetragonal phase and result in low 2Pr values.

Device modeling of two-steps oxygen anneal-based submicron InGaZnO back-end-of-line field-effect transistor enabling short-channel effects suppression.

Amorphous oxide semiconductor (AOS) field-effect transistors (FETs) have been integrated with complementary metal-oxide-semiconductor (CMOS) circuitry in the back end of line (BEOL) CMOS process; they are promising devices creating new and various functionalities. Therefore, it is urgent to understand the physics determining their scalability and establish a physics-based model for a robust device design of AOS BEOL FETs. However, the advantage emphasized to date has been mainly an ultralow leakage current of these devices. A device modeling that comprehensively optimizes the threshold voltage (VT), the short-channel effect (SCE), the subthreshold swing (SS), and the field-effect mobility (µFE) of short-channel AOS FETs has been rarely reported. In this study, the device modeling of two-steps oxygen anneal-based submicron indium-gallium-zinc-oxide (IGZO) BEOL FET enabling short-channel effects suppression is proposed and experimentally demonstrated. Both the process parameters determining the SCE and the device physics related to the SCE are elucidated through our modeling and a technology computer-aided design (TCAD) simulation. In addition, the procedure of extracting the model parameters is concretely supplied. Noticeably, the proposed device model and simulation framework reproduce all of the measured current-voltage (I-V), VT roll-off, and drain-induced barrier lowering (DIBL) characteristics according to the changes in the oxygen (O) partial pressure during the deposition of IGZO film, device structure, and channel length. Moreover, the results of an analysis based on the proposed model and the extracted parameters indicate that the SCE of submicron AOS FETs is effectively suppressed when the locally high oxygen-concentration region is used. Applying the two-step oxygen annealing to the double-gate (DG) FET can form this region, the beneficial effect of which is also proven through experimental results; the immunity to SCE is improved as the O-content controlled according to the partial O pressure during oxygen annealing increases. Furthermore, it is found that the essential factors in the device optimization are the subgap density of states (DOS), the oxygen content-dependent diffusion length of either the oxygen vacancy (VO) or O, and the separation between the top-gate edge and the source-drain contact hole. Our modeling and simulation results make it feasible to comprehensively optimize the device characteristic parameters, such as VT, SCE, SS, and µFE, of the submicron AOS BEOL FETs by independently controlling the lateral profile of the concentrations of VO and O in two-step oxygen anneal process.

Understanding the Origin of Metal Gate Work Function Shift and Its Impact on Erase Performance in 3D NAND Flash Memories.

We studied the metal gate work function of different metal electrode and high-k dielectric combinations by monitoring the flat band voltage shift with dielectric thicknesses using capacitance-voltage measurements. We investigated the impact of different thermal treatments on the work function and linked any shift in the work function, leading to an effective work function, to the dipole formation at the metal/high-k and/or high-k/SiO2 interface. We corroborated the findings with the erase performance of metal/high-k/ONO/Si (MHONOS) capacitors that are identical to the gate stack in three-dimensional (3D) NAND flash. We demonstrate that though the work function extraction is convoluted by the dipole formation, the erase performance is not significantly affected by it.

Understanding the Dual Nature of the Filament Dissolution in Conductive Bridging Devices.

The formation and rupture of conductive filaments (CFs) inside an insulating medium is used as hardware encoding of the state of a memory cell ("1" - "0") in filamentary-based conductive bridging memories. Currently accepted models explain the filament erase (reset) as the subtraction of conductive metal atoms from the CF; however, they do not fully account for the rich set of phenomena experimentally observed during the reset. The details of the filament erase are unraveled on the nanometer scale by means of an atomic force microscopy-based tomography technique enabling the 3D observation of erased CFs. "Non-broken" and "broken" CFs are observed, whereby the increase in resistance originates, respectively, from a constriction point in the current path and from an interrupted CF. We demonstrate that their existence and morphology can be related to the specific formation history of the CF, and we identify the physical volume of the CF as being mainly responsible for the type of filament erase.

Switching mechanism and reverse engineering of low-power Cu-based resistive switching devices.

In the recent past, filamentary-based resistive switching devices have emerged as predominant candidates for future non-volatile memory storage. Most of the striking characteristics of these devices are still limited by the high power consumption and poor understanding of the intimate resistive switching mechanism. In this study, we present an atomic scale study of the filament formation in CuTe-Al2O3 by using a conductive scanning probe tip to analyse the shape and dimensions of the filament. Filaments studied were either created within a normal device or locally formed while using the tip as the top electrode. We demonstrate that it is possible to create with C-AFM a filament with a signature identical to a device (i.e. two orders of magnitude resistance window, 10(4) s retention operating at 5 µA). This is obtained by a dedicated material and resistance selection for the conductive tip. The filamentary mechanism of fully processed devices is demonstrated and observed by C-AFM. Filaments created with C-AFM can be repeatedly cycled and the ON state presents a 20 nm highly conductive spot which can be repeatedly turned into a poorly conductive path in the OFF state.

Influence of carbon alloying on the thermal stability and resistive switching behavior of copper-telluride based CBRAM cells.

We report the improved thermal stability of carbon alloyed Cu0.6Te0.4 for resistive memory applications. Copper-tellurium-based memory cells show enhanced switching behavior, but the complex sequence of phase transformations upon annealing is disadvantageous for integration in a device. We show that addition of about 40 at % carbon to the Cu-telluride layer results in an amorphous material up to 360 °C. This material was then integrated in a TiN/Cu0.6Te0.4-C/Al2O3/Si resistive memory cell, and compared to pure Cu0.6Te0.4. Very attractive endurance (up to 1 × 10(3) cycles) and retention properties (up to 1 × 10(4) s at 85 °C) are observed. The enhanced thermal stability and good switching behavior make this material a promising candidate for integration in memory devices.