Compute in-Memory with Non-Volatile Elements for Neural Networks: A Review from a Co-Design Perspective.

Deep learning has become ubiquitous, touching daily lives across the globe. Today, traditional computer architectures are stressed to their limits in efficiently executing the growing complexity of data and models. Compute-in-memory (CIM) can potentially play an important role in developing efficient hardware solutions that reduce data movement from compute-unit to memory, known as the von Neumann bottleneck. At its heart is a cross-bar architecture with nodal non-volatile-memory elements that performs an analog multiply-and-accumulate operation, enabling the matrix-vector-multiplications repeatedly used in all neural network workloads. The memory materials can significantly influence final system-level characteristics and chip performance, including speed, power, and classification accuracy. With an over-arching co-design viewpoint, this review assesses the use of cross-bar based CIM for neural networks, connecting the material properties and the associated design constraints and demands to application, architecture, and performance. Both digital and analog memory are considered, assessing the status for training and inference, and providing metrics for the collective set of properties non-volatile memory materials will need to demonstrate for a successful CIM technology.

Ferroelectric Content-Addressable Memory Cells with IGZO Channel: Impact of Retention Degradation on the Multibit Operation.

Indium gallium zinc oxide (IGZO)-based ferroelectric thin-film transistors (FeTFTs) are being vigorously investigated for being deployed in computing-in-memory (CIM) applications. Content-addressable memories (CAMs) are the quintessential example of CIM, which conduct a parallel search over a queue or stack to obtain the matched entries for a given input data. CAM cells offer the ability for massively parallel searches in a single clock cycle throughout an entire CAM array for the input query, thereby enabling pattern matching and searching functionality. Therefore, CAM cells are used extensively for pattern matching or search operations in data-centric computing. This paper investigates the impact of retention degradation on IGZO-based FeTFT on the multibit operation in content CAM cell applications. We propose a scalable multibit 1FeTFT-1T-based CAM cell composed of only one FeTFT and one transistor, thus significantly improving the density and energy efficiency compared with conventional complementary metal-oxide-semiconductor (CMOS)-based CAM. We successfully demonstrate the operations of our proposed CAM with storage and search by exploiting the multilevel states of the experimentally calibrated IGZO-based FeTFT devices. We also investigate the impact of retention degradation on the search operation. Our proposed IGZO-based 3-bit and 2-bit CAM cell shows 104 s and 106 s retention, respectively. The single-bit CAM cell shows lifelong (10 years) retention.

Insulator-to-metal phase transition in a few-layered MoSe2 field effect transistor.

The metal-to-insulator phase transition (MIT) in low-dimensional materials and particularly two-dimensional layered semiconductors is exciting to explore due to the fact that it challenges the prediction that a two-dimensional system must be insulating at low temperatures. Thus, the exploration of MITs in 2D layered semiconductors expands the understanding of the underlying physics. Here we report the MIT of a few-layered MoSe2 field effect transistor under a gate bias (electric field) applied perpendicular to the MoSe2 layers. With low applied gate voltage, the conductivity as a function of temperature from 150 K to 4 K shows typical semiconducting to insulating character. Above a critical applied gate voltage, Vc, the conductivity becomes metallic (i.e., the conductivity increases continuously as a function of decreasing temperature). Evidence of a metallic state was observed using an applied gate voltage or, equivalently, increasing the density of charge carriers within the 2D channel. We analyzed the nature of the phase transition using percolation theory, where conductivity scales with the density of charge carriers as σ ∝ (n - nc)δ. The critical exponent for a percolative phase transition, δ(T), has values ranging from 1.34 (at T = 150 K) to 2 (T = 20 K), which is close to the theoretical value of 1.33 for percolation to occur. Thus we conclude that the MIT in few-layered MoSe2 is driven by charge carrier percolation. Furthermore, the conductivity does not scale with temperature, which is a hallmark of a quantum critical phase transition.

Nanoporous Dielectric Resistive Memories Using Sequential Infiltration Synthesis.

Resistance switching in metal-insulator-metal structures has been extensively studied in recent years for use as synaptic elements for neuromorphic computing and as nonvolatile memory elements. However, high switching power requirements, device variabilities, and considerable trade-offs between low operating voltages, high on/off ratios, and low leakage have limited their utility. In this work, we have addressed these issues by demonstrating the use of ultraporous dielectrics as a pathway for high-performance resistive memory devices. Using a modified atomic layer deposition based technique known as sequential infiltration synthesis, which was developed originally for improving polymer properties such as enhanced etch resistance of electron-beam resists and for the creation of films for filtration and oleophilic applications, we are able to create ∼15 nm thick ultraporous (pore size ∼5 nm) oxide dielectrics with up to 73% porosity as the medium for filament formation. We show, using the Ag/Al2O3 system, that the ultraporous films result in ultrahigh on/off ratio (>109) at ultralow switching voltages (∼±600 mV) that are 10× smaller than those for the bulk case. In addition, the devices demonstrate fast switching, pulsed endurance up to 1 million cycles. and high temperature (125 °C) retention up to 104 s, making this approach highly promising for large-scale neuromorphic and memory applications. Additionally, this synthesis methodology provides a compatible, inexpensive route that is scalable and compatible with existing semiconductor nanofabrication methods and materials.

Silicon compatible Sn-based resistive switching memory.

Large banks of cheap, fast, non-volatile, energy efficient, scalable solid-state memories are an increasingly essential component for today's data intensive computing. Conductive-bridge random access memory (CBRAM) - which involves voltage driven formation and dissolution of Cu or Ag filaments in a Cu (or Ag) anode/dielectric (HfO2 or Al2O3)/inert cathode device - possesses the necessary attributes to fit the requirements. Cu and Ag are, however, fast diffusers and known contaminants in silicon microelectronics. Herein, employing a criterion for electrode metal selection applicable to cationic filamentary devices and using first principles calculations for estimating diffusion barriers in HfO2, we identify tin (Sn) as a rational, silicon CMOS compatible replacement for Cu and Ag anodes in CBRAM devices. We then experimentally fabricate Sn based CBRAM devices and demonstrate very fast, steep-slope memory switching as well as threshold switching, comparable to Cu or Ag based devices. Furthermore, time evolution of the cationic filament formation along with the switching mechanism is discussed based on time domain measurements (I vs. t) carried out under constant voltage stress. The time to threshold is shown to be a function of both the voltage stress (Vstress) as well as the initial leakage current (I0) through the device.