A Configurable and Fully Synthesizable RTL-Based Convolutional Neural Network for Biosensor Applications.

This paper presents a register-transistor level (RTL) based convolutional neural network (CNN) for biosensor applications. Biosensor-based diseases detection by DNA identification using biosensors is currently needed. We proposed a synthesizable RTL-based CNN architecture for this purpose. The adopted technique of parallel computation of multiplication and accumulation (MAC) approach optimizes the hardware overhead by significantly reducing the arithmetic calculation and achieves instant results. While multiplier bank sharing throughout the convolutional operation with fully connected operation significantly reduces the implementation area. The CNN model is trained in MATLAB® on MNIST® handwritten dataset. For validation, the image pixel array from MNIST® handwritten dataset is applied on proposed RTL-based CNN architecture for biosensor applications in ModelSim®. The consistency is checked with multiple test samples and 92% accuracy is achieved. The proposed idea is implemented in 28 nm CMOS technology. It occupies 9.986 mm2 of the total area. The power requirement is 2.93 W from 1.8 V supply. The total time taken is 8.6538 ms.

A Low-Power Analog Processor-in-Memory-Based Convolutional Neural Network for Biosensor Applications.

This paper presents an on-chip implementation of an analog processor-in-memory (PIM)-based convolutional neural network (CNN) in a biosensor. The operator was designed with low power to implement CNN as an on-chip device on the biosensor, which consists of plates of 32 × 32 material. In this paper, 10T SRAM-based analog PIM, which performs multiple and average (MAV) operations with multiplication and accumulation (MAC), is used as a filter to implement CNN at low power. PIM proceeds with MAV operations, with feature extraction as a filter, using an analog method. To prepare the input feature, an input matrix is formed by scanning a 32 × 32 biosensor based on a digital controller operating at 32 MHz frequency. Memory reuse techniques were applied to the analog SRAM filter, which is the core of low power implementation, and in order to accurately grasp the MAC operational efficiency and classification, we modeled and trained numerous input features based on biosignal data, confirming the classification. When the learned weight data was input, 19 mW of power was consumed during analog-based MAC operation. The implementation showed an energy efficiency of 5.38 TOPS/W and was differentiated through the implementation of 8 bits of high resolution in the 180 nm CMOS process.

A Design of Adaptive Control and Communication Protocol for SWIPT System in 180 nm CMOS Process for Sensor Applications.

This paper presents an adaptive control and communication protocol (ACCP) for the ultra-low power simultaneous wireless information and power transfer (SWIPT) system for sensor applications. The SWIPT system-related operations depend on harvested radio frequency (RF) energy from the ambient environment. The necessary power for SWIPT system operation is not always available and it depends on the available RF energy in the ambient environment, transmitted RF power from the SWIPT transmitter, and the distance from the transmitter and channel conditions. Thus, an efficient control and communication protocol is required which can control the SWIPT system for sensor applications which mainly consists of a transmitter and a receiver. Multiple data frame structures are used to optimize the exchange of bits for the communication and control of the SWIPT system. Both SWIPT transmitter and receiver are capable of using multiple modulation schemes which can be switched depending on the channel condition and the available RF energy in the ambient environment. This provides support for automatic switching between the time switching scheme and power splitting scheme for the distribution of received RF power in the SWIPT receiver. It also adjusts the digital clock frequency at the SWIPT receiver according to the harvested power level to optimize the power consumption. The SWIPT receiver controller with ACCP is implemented in 180 nm CMOS technology. The RF frequency of the SWIPT operation is 5.8 GHz. Digital clock frequency at the SWIPT receiver can be adjusted between 32 kHz and 2 MHz which provides data rates from 8 to 500 kbps, respectively. The power consumption and area utilization are 12.3 µW and 0.81 mm².