Dopant Engineering of Hafnia-Based Ferroelectrics for Long Data Retention and High Thermal Stability.

Hafnia-based ferroelectrics have gained much attention because they can be used in highly scaled, advanced complementary metal-oxide semiconductor (CMOS) memory devices. However, thermal stability should be considered when integrating hafnia-based ferroelectric transistors in advanced CMOS devices, as they can be exposed to high-temperature processes. This work proposed that doping of Al in hafnia-based ferroelectric material can lead to high thermal stability. A ferroelectric capacitor based on Al-doped hafnia, which can be used for one-transistor-one-capacitor applications, exhibits stable operation even after annealing at 900 °C. Moreover, it demonstrates that the ferroelectric transistors based on Al-doped hafnia for one-transistor applications, such as ferroelectric NAND, retain their memory states for 10 years at 100 °C. This study presents a practical method to achieve thermally stable ferroelectric memories capable of enduring high-temperature processes and operation conditions.

Demonstration of the threshold-switching memory devices using EMIm(AlCl3)Cl and ZnO for neuromorphic applications.

The threshold-switching behaviors of the synapses lead to energy-efficient operation in the neural computing system. Here, we demonstrated the threshold-switching memory devices by inserting the ZnO layer into the ionic synaptic devices. The EMIm(AlCl3)Cl is utilized as the electrolyte because its conductance can be tuned by the charge states of the Al-based ions. The redox reactions of the Al ions in the electrolyte can lead to the analog resistive switching characteristics, such as excitatory postsynaptic current, paired-pulse facilitation, potentiation, and depression. By inserting the ZnO layer into the EMIm(AlCl3)-based ionic synaptic devices, the threshold switching behaviors are demonstrated. Using the resistivity difference between ZnO and EMIm(AlCl3)Cl, the analog resistive switching behaviors are tunned as the threshold-switching behaviors. The threshold-switching behaviors are achieved by applying the spike stimuli to the device. Demonstration of the threshold-switching behaviors of the ionic synaptic devices has a possibility to achieve high energy-efficiency for the ion-based artificial synapses.

Voltage-Tunable Ultra-Steep Slope Atomic Switch with Selectivity over 1010.

Atomic switch-based selectors, which utilize the formation of conductive filaments by the migration of ions, are researched for cross-point array architecture due to their simple structure and high selectivity. However, the difficulty in controlling the formation of filaments causes uniformity and reliability issues. Here, a multilayer selector with Pt/Ag-doped ZnO/ZnO/Ag-doped ZnO/Pt structure by the sputtering process is presented. A multilayer structure enables control of the filament formation by preventing excessive influx of Ag ions. The multilayer selector device exhibits a high on-current density of 2 MA cm-2 , which can provide sufficient current for the operation with the memory device. Also, the device exhibits high selectivity of 1010 and a low off-current of 10-13 A. The threshold voltage of selector devices can be controlled by modulating the thickness of the ZnO layer. By connecting a multilayer selector device to a resistive switching memory, the leakage current of the memory device can be reduced. These results demonstrate that a multilayer structure can be used in a selector device to improve selectivity and reliability for use in high-density memory devices.

Ferroelectric Analog Synaptic Transistors.

Neuromorphic computing is a promising alternative to conventional computing systems as it could enable parallel computation and adaptive learning process. However, the development of energy efficient neuromorphic hardware systems has been hindered by the limited performance of analog synaptic devices. Here, we demonstrate the analog conductance modulation behavior in the ferroelectric thin-film transistors (FeTFT) that have the nanoscale ferroelectric material and oxide semiconductors. Accurate control of polarization changes in the nanoscale ferroelectric layer induces conductance modulation to demonstrate linear potentiation and depression characteristics of FeTFTs. Our devices show potentiation and depression properties, including high linearity, multiple states, and small cycle-to-cycle/device-to-device variations. In simulations with measured properties, a neuromorphic system with FeTFT achieves 91.1% recognition accuracy of handwritten digits. This work may provide a way to realize the neuromorphic hardware systems that use FeTFTs as the synaptic devices.

Flexible resistive switching memory with a Ni/CuO x /Ni structure using an electrochemical deposition process.

Flexible resistive switching memory (ReRAM) devices were fabricated with a Ni/CuO x /Ni structure. Fabrication involved simple and low-cost electrochemical deposition of electrodes and resistive switching layers on a polyethylene terephthalate substrate. The devices exhibited reproducible and reliable ReRAM characteristics. Bipolar resistive switching was observed in flexible Ni/CuO x /Ni-based ReRAM devices with low operation voltages. The reliability of the devices was confirmed by data retention, endurance, and cyclic bending measurements. The processes for fabrication of flexible ReRAM devices were based on simple-solution, bottom-up growth and they can be performed at low temperatures. Therefore, the methods presented in this work could be a viable solution for fabricating flexible non-volatile memory devices in the future.

All-solution-processed nonvolatile flexible nano-floating gate memory devices.

Organic semiconductors have great potential for future electronic applications owing to their inherent flexibility, low cost, light weight and ability to easily cover large areas. However, all of these advantageous material properties can only be harnessed if simple, cheap and low-temperature fabrication processes, which exclude the need for vacuum deposition and are compatible with flexible plastic substrates, are employed. There are a few solution-based techniques such as spin-coating and inkjet printing that meet the above criteria. In this paper, we describe a novel all-solution-processed nonvolatile memory device fabricated on a flexible plastic substrate. The source, drain and gate electrodes were printed using an inkjet printer with a conducting organic solution, while the semiconducting layer was spin-coated with an n-type polymer. The charge-trapping layer was composed of spin-coated reduced graphene oxide (rGO), which was prepared in the form of a solution using Hummer's method. The fabricated device was characterized in order to confirm the memory characteristics. Device parameters such as threshold voltage shift, retention/endurance characteristics, mechanical robustness and reliability upon bending were also analyzed.

Unlocking large memory windows and 16-level data per cell memory operations in hafnia-based ferroelectric transistors.

Ferroelectric transistors based on hafnia-based ferroelectrics exhibit tremendous potential as next-generation memories owing to their high-speed operation and low power consumption. Nevertheless, these transistors face limitations in terms of memory window, which directly affects their ability to support multilevel characteristics in memory devices. Furthermore, the absence of an efficient operational technique capable of achieving multilevel characteristics has hindered their development. To address these challenges, we present a gate stack engineering method and an efficient operational approach for ferroelectric transistors to achieve 16-level data per cell operation. By using the suggested engineering method, we demonstrate the attainment of a substantial memory window of 10 V without increasing the device area. Additionally, we propose a displacement current control method, facilitating one-shot programming to the desired state. Remarkably, we suggest the compatibility of these proposed methods with three-dimensional (3D) structures. This study underscores the potential of ferroelectric transistors for next-generation 3D memory applications.

Exploring Disturb Characteristics in 2D and 3D Ferroelectric NAND Memory Arrays for Next-Generation Memory Technology.

Ferroelectric transistors are considered promising for next-generation 3D NAND technology due to their lower power consumption and faster operation compared to conventional charge-trap flash memories. However, ensuring their suitability for such applications requires a thorough investigation of array-scale reliability. This study specifically examines the suitability of hafnia-based ferroelectric transistors for advanced 3D NAND applications, with a specific focus on establishing a disturb-free voltage scheme to ensure the reliability of ferroelectric transistors within the array. Our key finding highlights the crucial role of optimal pass voltage in achieving disturb-free operation in both 2D and 3D ferroelectric NAND arrays. Additionally, the study indicates that read disturb remains negligible when an appropriate read voltage is applied. These insights provide a practical strategy for achieving reliable operation in 2D and 3D ferroelectric NAND, highlighting the potential of hafnia-based ferroelectric materials to meet the evolving requirements of high-density and reliable NAND flash memory applications.

Ferroelectric Transistors for Memory and Neuromorphic Device Applications.

Ferroelectric materials have been intensively investigated for high-performance nonvolatile memory devices in the past decades, owing to their nonvolatile polarization characteristics. Ferroelectric memory devices are expected to exhibit lower power consumption and higher speed than conventional memory devices. However, non-complementary metal-oxide-semiconductor (CMOS) compatibility and degradation due to fatigue of traditional perovskite-based ferroelectric materials have hindered the development of high-density and high-performance ferroelectric memories in the past. The recently developed hafnia-based ferroelectric materials have attracted immense attention in the development of advanced semiconductor devices. Because hafnia is typically used in CMOS processes, it can be directly incorporated into current semiconductor technologies. Additionally, hafnia-based ferroelectrics show high scalability and large coercive fields that are advantageous for high-density memory devices. This review summarizes the recent developments in ferroelectric devices, especially ferroelectric transistors, for next-generation memory and neuromorphic applications. First, the types of ferroelectric memories and their operation mechanisms are reviewed. Then, issues limiting the realization of high-performance ferroelectric transistors and possible solutions are discussed. The experimental demonstration of ferroelectric transistor arrays, including 3D ferroelectric NAND and its operation characteristics, are also reviewed. Finally, challenges and strategies toward the development of next-generation memory and neuromorphic applications based on ferroelectric transistors are outlined.

Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks.

Hardware-based neural networks (NNs) can provide a significant breakthrough in artificial intelligence applications due to their ability to extract features from unstructured data and learn from them. However, realizing complex NN models remains challenging because different tasks, such as feature extraction and classification, should be performed at different memory elements and arrays. This further increases the required number of memory arrays and chip size. Here, we propose a three-dimensional ferroelectric NAND (3D FeNAND) array for the area-efficient hardware implementation of NNs. Vector-matrix multiplication is successfully demonstrated using the integrated 3D FeNAND arrays, and excellent pattern classification is achieved. By allocating each array of vertical layers in 3D FeNAND as the hidden layer of NN, each layer can be used to perform different tasks, and the classification of color-mixed patterns is achieved. This work provides a practical strategy to realize high-performance and highly efficient NN systems by stacking computation components vertically.

Defect Engineering of Hafnia-Based Ferroelectric Materials for High-Endurance Memory Applications.

Zirconium-doped hafnium oxide (HfZrOx) is one of the promising ferroelectric materials for next-generation memory applications. To realize high-performance HfZrOx for next-generation memory applications, the formation of defects in HfZrOx, including oxygen vacancies and interstitials, needs to be optimized, as it can affect the polarization and endurance characteristics of HfZrOx. In this study, we investigated the effects of ozone exposure time during the atomic layer deposition (ALD) process on the polarization and endurance characteristics of 16-nm-thick HfZrOx. HfZrOx films showed different polarization and endurance characteristics depending on the ozone exposure time. HfZrOx deposited using the ozone exposure time of 1 s showed small polarization and large defect concentration. The increase of the ozone exposure time to 2.5 s could reduce the defect concentration and improve the polarization characteristics of HfZrOx. When the ozone exposure time further increased to 4 s, a reduction of polarization was observed in HfZrOx due to the formation of oxygen interstitials and non-ferroelectric monoclinic phases. HfZrOx, with an ozone exposure time of 2.5 s, exhibited the most stable endurance characteristics because of the low initial defect concentration in HfZrOx, which was confirmed by the leakage current analysis. This study shows that the ozone exposure time of ALD needs to be controlled to optimize the formation of defects in HfZrOx films for the improvement of polarization and endurance characteristics.

Inorganic Perovskite Quantum Dot-Mediated Photonic Multimodal Synapse.

Artificial synapse is the basic unit of a neuromorphic computing system. However, there is a need to explore suitable synaptic devices for the emulation of synaptic dynamics. This study demonstrates a photonic multimodal synaptic device by implementing a perovskite quantum dot charge-trapping layer in the organic poly(3-hexylthiophene-2,5-diyl) (P3HT) channel transistor. The proposed device presents favorable band alignment that facilitates spatial separation of photogenerated charge carriers. The band alignment serves as the basis of optically induced charge trapping, which enables nonvolatile memory characteristics in the device. Furthermore, high photoresponse and excellent synaptic characteristics, such as short-term plasticity, long-term plasticity, excitatory postsynaptic current, and paired-pulse facilitation, are obtained through gate voltage regulation. Photosynaptic characteristics obtained from the device showed a multiwavelength response and a large dynamic range (∼103) that is suitable for realizing a highly accurate artificial neural network. Moreover, the device showed nearly linear synaptic weight update characteristics with incremental depression electric gate pulse. The simulation based on the experimental data showed excellent pattern recognition accuracy (∼85%) after 120 epochs. The results of this study demonstrate the feasibility of the device as an optical synapse in the next-generation neuromorphic system.

Recent Advances and Future Prospects for Memristive Materials, Devices, and Systems.

Memristive technology has been rapidly emerging as a potential alternative to traditional CMOS technology, which is facing fundamental limitations in its development. Since oxide-based resistive switches were demonstrated as memristors in 2008, memristive devices have garnered significant attention due to their biomimetic memory properties, which promise to significantly improve power consumption in computing applications. Here, we provide a comprehensive overview of recent advances in memristive technology, including memristive devices, theory, algorithms, architectures, and systems. In addition, we discuss research directions for various applications of memristive technology including hardware accelerators for artificial intelligence, in-sensor computing, and probabilistic computing. Finally, we provide a forward-looking perspective on the future of memristive technology, outlining the challenges and opportunities for further research and innovation in this field. By providing an up-to-date overview of the state-of-the-art in memristive technology, this review aims to inform and inspire further research in this field.

Size effects on the stabilization and growth of tetragonal ZrO2 crystallites in a nanotubular structure.

The size effects on the stabilization of ZrO2 polymorphs in nanoscale and the growth behavior of their crystallites in 1-D nanotubular structures were investigated. Polycrystalline nanotubular structures of ZrO2 with tetragonal nanocrystallites were fabricated using nanoporous polycarbonate (PC) templates and atomic layer deposition (ALD). The as-prepared ZrO2 nanotubes showed polycrystalline structures of stabilized tetragonal polymorphs at room temperature. The wall thickness of the ZrO2 nanotubes was well controlled by the number of ALD cycles. Faster growth of the tetragonal nanocrystallites was observed in the nanotubes with a 50 nm outer diameter, than those of 200 nm. The Gibbs-Thompson relation can be used to explain the observed nanosize effects on the growth of the tetragonal ZrO2 nanocrystallites.

Memory effect of low-temperature processed ZnO thin-film transistors having metallic nanoparticles as charge trapping elements.

In this study, non-volatile memory effect was characterized using the single-transistor-based memory devices based on self-assembled gold nanoparticles (AuNP) as the charge trapping elements and atomic-layer deposited ZnO as the channel layer. The fabricated memory devices showed controllable and reliable threshold voltage shifts according to the program/erase operations that resulted from the charging/discharging of charge carriers in the charge trapping elements. Reliable non-volatile memory properties were also confirmed by the endurance and data retention measurements. The low temperature processes of the key device elements, i.e., AuNP charge trapping layer and ZnO channel layer, enable the use of this device structure to the transparent/flexible non-volatile memory applications in the near future.

High performance flexible organic thin film transistors (OTFTs) with octadecyltrichlorsilane/ Al2O3/poly(4-vinylphenol) multilayer insulators.

The incorporation of a thin, atomic layer deposited Al2O3 layer in between a spin-coated poly-4-vinyl phenol (PVP) organic layer and octadecyltrichlorsilane (OTS) in the multilayer gate dielectric for pentacene organic thin film transistors on a n(+)-Si substrate reduced the gate leakage current and thereby significantly enhanced the current on/off ratio up to 2.8 x 10(6). Addition of the OTS monolayer on the UV-treated Al2O3 improved the crystallinity of the pentacene layer, where the OTS/UV-treated Al2O3 surfaces increased their contact angles to 100 degrees. X-ray diffraction (XRD) analysis revealed a more intense (001) crystal reflectance of pentacene deposited on OTS/UV-treated Al2O3 surface than that on OTS/Al2O3 surface. Moreover, the improved pentacene layer contributed to the field effect mobility (0.4 cm2/Vs) and subsequently improved the electrical performances of organic thin film transistor (OTFT) devices. This PVP/UV treated Al2O3/OTS multilayer gate dielectric stack was superior to those of the device with the single PVP gate dielectrics due to the improved crystallinity of pentacene.

Metal Halide Perovskite-Based Memristors for Emerging Memory Applications.

There is an increased demand for next-generation memory devices with high density and fast operation speed to replace conventional memory devices. Memristors are promising candidates for next-generation memory devices because of their scalability, stable data retention, low power consumption, and fast operation. Among the various types of memristors, halide perovskites exhibit potential as emerging materials for memristors by using hysteresis based on the movement of defects or ions in halide perovskites. However, research on the implementation of perovskite materials as memristors is in its early stages; some challenges and problems must be solved to enable the practical application of halide perovskites for next-generation memory devices. From this perspective, we highlight the recent progress in memristors that use halide perovskites. Moreover, we introduce a strategy to enhance the performance and analyze the operation mechanism of memory devices that use halide perovskites. Finally, we summarize the challenges in the development of device technology to use halide perovskites in next-generation memory devices.

Controlling the Grain Size of Dion-Jacobson-Phase Two-Dimensional Layered Perovskite for Memory Application.

Organic-inorganic halide perovskites (OIHPs) have emerged as an active layer for resistive switching memory (RSM). Among various OIHPs, two-dimensional OIHPs are advantageous in RSMs because of their stability. This stability can be further improved using two-dimensional Dion-Jacobson OIHPs. Moreover, OIHP-based RSMs operated by the formation of halide-ion filaments are affected by grain boundaries because they can act as a shortcut for ion migration. Therefore, it is essential to control the grains in OIHPs for reliable memory operation. Here, we present RSMs using Dion-Jacobson OIHP with controlled grain sizes. The grain sizes of the OIHP are effectively controlled by adjusting the ratio of the N,N-dimethylformamide and dimethyl sulfoxide. The controlled grain sizes can modulate the paths for halide ion migration, which enables the change of the on/off ratio in RSM. In addition, cross-point array structure is essential for high-density memory applications. However, in the cross-point array structure, unwanted current flow through unselected memory cells can happen due to sneak-current paths, so it is necessary to suppress leakage current from neighboring cells by adopting selector devices. We demonstrate the application of selector devices to OIHP-based RSMs to prevent sneak current paths. These results provide the potential of OIHP for use in high-density memory applications.

Emulating the Signal Transmission in a Neural System Using Polymer Membranes.

Neurons are vital components of the brain. When stimulated by neurotransmitters at the dendrites, neurons deliver signals as changes in the membrane potential by ion movement. The signal transmission of a nervous system exhibits a high energy efficiency. These characteristics of neurons are being exploited to develop efficient neuromorphic computing systems. In this study, we develop chemical synapses for neuromorphic devices and emulate the signaling processes in a nervous system using a polymer membrane, in which the ionic permeability can be controlled. The polymer membrane comprises poly(diallyl-dimethylammonium chloride) and poly(3-sulfopropyl acrylate potassium salt), which have positive and negative charges, respectively. The ionic permeability of the polymer membrane is controlled by the injection of a neurotransmitter solution. This device emulates the signal transmission behavior of biological neurons depending on the concentration of the injected neurotransmitter solution. The proposed artificial neuronal signaling device can facilitate the development of bio-realistic neuromorphic devices.

CMOS-compatible compute-in-memory accelerators based on integrated ferroelectric synaptic arrays for convolution neural networks.

Convolutional neural networks (CNNs) have gained much attention because they can provide superior complex image recognition through convolution operations. Convolution processes require repeated multiplication and accumulation operations, which are difficult tasks for conventional computing systems. Compute-in-memory (CIM) that uses parallel data processing is an ideal device structure for convolution operations. CIM based on two-terminal synaptic devices with a crossbar structure has been developed, but unwanted leakage current paths and the high-power consumption remain as the challenges. Here, we demonstrate integrated ferroelectric thin-film transistor (FeTFT) synaptic arrays that can provide efficient parallel programming and data processing for CNNs by the selective and accurate control of polarization in the ferroelectric layer. In addition, three-terminal FeTFTs can act as both nonvolatile memory and access device, which tackle issues from two-terminal devices. An integrated FeTFT synaptic array with parallel programming capabilities can perform convolution operations to extract image features with a high-recognition accuracy.