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1.
Nanotechnology ; 25(14): 145302, 2014 Apr 11.
Artigo em Inglês | MEDLINE | ID: mdl-24633016

RESUMO

We investigate the ability to introduce strain into atomic-scale silicon device fabrication by performing hydrogen lithography and creating electrically active phosphorus δ-doped silicon on strained silicon-on-insulator (sSOI) substrates. Lithographic patterns were obtained by selectively desorbing hydrogen atoms from a H resist layer adsorbed on a clean, atomically flat sSOI(001) surface with a scanning tunnelling microscope tip operating in ultra-high vacuum. The influence of the tip-to-sample bias on the lithographic process was investigated allowing us to pattern feature-sizes from several microns down to 1.3 nm. In parallel we have investigated the impact of strain on the electrical properties of P:Si δ-doped layers. Despite the presence of strain inducing surface variations in the silicon substrate we still achieve high carrier densities (>1.0 × 10(14) cm(-2)) with mobilities of ∼100 cm(2) V(-1) s(-1). These results open up the possibility of a scanning-probe lithography approach to the fabrication of strained atomic-scale devices in silicon.

2.
Nanotechnology ; 24(4): 045303, 2013 Feb 01.
Artigo em Inglês | MEDLINE | ID: mdl-23291418

RESUMO

Three-dimensional (3D) control of dopant profiles in silicon is a critical requirement for fabricating atomically precise transistors. We demonstrate conductance modulation through an atomic scale 3 nm wide δ-doped silicon-phosphorus wire using a vertically separated epitaxial doped Si:P top-gate. We show that intrinsic crystalline silicon grown at low temperatures (∼250 °C) serves as an effective gate dielectric permitting us to achieve large gate ranges (∼2.6 V) with leakage currents below 1 pA. Combining scanning tunneling lithography for precise lateral confinement, with monolayer doping and low temperature epitaxial overgrowth for precise vertical confinement, we can realize multiple layers of nano-patterned dopants in a single crystal material. These results demonstrate the viability of highly doped, vertically separated epitaxial gates in an all-crystalline architecture with long-term implications for monolithic 3D silicon circuits and for the realization of atomically precise donor architectures for quantum computing.


Assuntos
Cristalização/métodos , Nanotubos/química , Nanotubos/ultraestrutura , Silício/química , Condutividade Elétrica , Gases/química , Substâncias Macromoleculares/química , Teste de Materiais , Conformação Molecular , Tamanho da Partícula , Propriedades de Superfície
3.
Sci Rep ; 7(1): 12790, 2017 10 06.
Artigo em Inglês | MEDLINE | ID: mdl-28986546

RESUMO

As semiconductor electronics keep shrinking, functionality depends on individual atomic scale surface and interface features that may change as voltages are applied. In this work we demonstrate a novel device platform that allows scanning tunneling microscopy (STM) imaging with atomic scale resolution across a device simultaneously with full electrical operation. The platform presents a significant step forward as it allows STM to be performed everywhere on the device surface and high temperature processing in reactive gases of the complete device. We demonstrate the new method through proof of principle measurements on both InAs and GaAs nanowire devices with variable biases up to 4 V. On InAs nanowires we observe a surprising removal of atomic defects and smoothing of the surface morphology under applied bias, in contrast to the expected increase in defects and electromigration-related failure. As we use only standard fabrication and scanning instrumentation our concept is widely applicable and opens up the possibility of fundamental investigations of device surface reliability as well as new electronic functionality based on restructuring during operation.

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