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1.
Nat Nanotechnol ; 19(7): 970-977, 2024 Jul.
Artigo em Inglês | MEDLINE | ID: mdl-39043826

RESUMO

The semiconductor industry is transitioning to the 'More Moore' era, driven by the adoption of three-dimensional (3D) integration schemes surpassing the limitations of traditional two-dimensional scaling. Although innovative packaging solutions have made 3D integrated circuits (ICs) commercially viable, the inclusion of through-silicon vias and microbumps brings about increased area overhead and introduces parasitic capacitances that limit overall performance. Monolithic 3D integration (M3D) is regarded as the future of 3D ICs, yet its application faces hurdles in silicon ICs due to restricted thermal processing budgets in upper tiers, which can degrade device performance. To overcome these limitations, emerging materials like carbon nanotubes and two-dimensional semiconductors have been integrated into the back end of silicon ICs. Here we report the M3D integration of complementary WSe2 FETs, in which n-type FETs are placed in tier 1 and p-type FETs are placed in tier 2. In particular, we achieve dense and scaled integration through 300 nm vias with a pitch of <1 µm, connecting more than 300 devices in tiers 1 and 2. Moreover, we have effectively implemented vertically integrated logic gates, encompassing inverters, NAND gates and NOR gates. Our demonstration highlights the two-dimensional materials' role in advancing M3D integration in complementary metal-oxide-semiconductor circuits.

2.
ACS Nano ; 17(20): 19709-19723, 2023 Oct 24.
Artigo em Inglês | MEDLINE | ID: mdl-37812500

RESUMO

n-type field effect transistors (FETs) based on two-dimensional (2D) transition-metal dichalcogenides (TMDs) such as MoS2 and WS2 have come close to meeting the requirements set forth in the International Roadmap for Devices and Systems (IRDS). However, p-type 2D FETs are dramatically lagging behind in meeting performance standards. Here, we adopt a three-pronged approach that includes contact engineering, channel length (Lch) scaling, and monolayer doping to achieve high performance p-type FETs based on synthetic WSe2. Using electrical measurements backed by atomistic imaging and rigorous analysis, Pd was identified as the favorable contact metal for WSe2 owing to better epitaxy, larger grain size, and higher compressive strain, leading to a lower Schottky barrier height. While the ON-state performance of Pd-contacted WSe2 FETs was improved by ∼10× by aggressively scaling Lch from 1 µm down to ∼20 nm, ultrascaled FETs were found to be contact limited. To reduce the contact resistance, monolayer tungsten oxyselenide (WOxSey) obtained using self-limiting oxidation of bilayer WSe2 was used as a p-type dopant. This led to ∼5× improvement in the ON-state performance and ∼9× reduction in the contact resistance. We were able to achieve a median ON-state current as high as ∼10 µA/µm for ultrascaled and doped p-type WSe2 FETs with Pd contacts. We also show the applicability of our monolayer doping strategy to other 2D materials such as MoS2, MoTe2, and MoSe2.

3.
Nat Nanotechnol ; 18(11): 1295-1302, 2023 Nov.
Artigo em Inglês | MEDLINE | ID: mdl-37500779

RESUMO

Epitaxial growth of two-dimensional transition metal dichalcogenides on sapphire has emerged as a promising route to wafer-scale single-crystal films. Steps on the sapphire act as sites for transition metal dichalcogenide nucleation and can impart a preferred domain orientation, resulting in a substantial reduction in mirror twins. Here we demonstrate control of both the nucleation site and unidirectional growth direction of WSe2 on c-plane sapphire by metal-organic chemical vapour deposition. The unidirectional orientation is found to be intimately tied to growth conditions via changes in the sapphire surface chemistry that control the step edge location of WSe2 nucleation, imparting either a 0° or 60° orientation relative to the underlying sapphire lattice. The results provide insight into the role of surface chemistry on transition metal dichalcogenide nucleation and domain alignment and demonstrate the ability to engineer domain orientation over wafer-scale substrates.

4.
ACS Nano ; 15(12): 19815-19827, 2021 Dec 28.
Artigo em Inglês | MEDLINE | ID: mdl-34914350

RESUMO

The rapid proliferation of security compromised hardware in today's integrated circuit (IC) supply chain poses a global threat to the reliability of communication, computing, and control systems. While there have been significant advancements in detection and avoidance of security breaches, current top-down approaches are mostly inadequate, inefficient, often inconclusive, and resource extensive in time, energy, and cost, offering tremendous scope for innovation in this field. Here, we introduce an energy and area efficient non-von Neumann hardware platform providing comprehensive and bottom-up security solutions by exploiting inherent device-to-device variation, electrical programmability, and persistent photoconductivity demonstrated by atomically thin two-dimensional memtransistors. We realize diverse security primitives including physically unclonable function, anticounterfeit measures, intellectual property (IP) watermarking, and IC camouflaging to prevent false authentication, detect recycled and remarked ICs, protect IP theft, and stop reverse engineering of ICs.

5.
Nat Commun ; 12(1): 2143, 2021 04 09.
Artigo em Inglês | MEDLINE | ID: mdl-33837210

RESUMO

Spiking neural networks (SNNs) promise to bridge the gap between artificial neural networks (ANNs) and biological neural networks (BNNs) by exploiting biologically plausible neurons that offer faster inference, lower energy expenditure, and event-driven information processing capabilities. However, implementation of SNNs in future neuromorphic hardware requires hardware encoders analogous to the sensory neurons, which convert external/internal stimulus into spike trains based on specific neural algorithm along with inherent stochasticity. Unfortunately, conventional solid-state transducers are inadequate for this purpose necessitating the development of neural encoders to serve the growing need of neuromorphic computing. Here, we demonstrate a biomimetic device based on a dual gated MoS2 field effect transistor (FET) capable of encoding analog signals into stochastic spike trains following various neural encoding algorithms such as rate-based encoding, spike timing-based encoding, and spike count-based encoding. Two important aspects of neural encoding, namely, dynamic range and encoding precision are also captured in our demonstration. Furthermore, the encoding energy was found to be as frugal as ≈1-5 pJ/spike. Finally, we show fast (≈200 timesteps) encoding of the MNIST data set using our biomimetic device followed by more than 91% accurate inference using a trained SNN.


Assuntos
Materiais Biomiméticos , Redes Neurais de Computação , Transistores Eletrônicos , Potenciais de Ação/fisiologia , Algoritmos , Biomimética/instrumentação , Conjuntos de Dados como Assunto , Humanos , Rede Nervosa/citologia , Rede Nervosa/fisiologia , Células Receptoras Sensoriais/fisiologia , Córtex Visual/citologia , Córtex Visual/fisiologia
6.
Nat Commun ; 11(1): 5474, 2020 10 29.
Artigo em Inglês | MEDLINE | ID: mdl-33122647

RESUMO

Memristive crossbar architectures are evolving as powerful in-memory computing engines for artificial neural networks. However, the limited number of non-volatile conductance states offered by state-of-the-art memristors is a concern for their hardware implementation since trained weights must be rounded to the nearest conductance states, introducing error which can significantly limit inference accuracy. Moreover, the incapability of precise weight updates can lead to convergence problems and slowdown of on-chip training. In this article, we circumvent these challenges by introducing graphene-based multi-level (>16) and non-volatile memristive synapses with arbitrarily programmable conductance states. We also show desirable retention and programming endurance. Finally, we demonstrate that graphene memristors enable weight assignment based on k-means clustering, which offers greater computing accuracy when compared with uniform weight quantization for vector matrix multiplication, an essential component for any artificial neural network.

7.
Nat Commun ; 11(1): 4406, 2020 09 02.
Artigo em Inglês | MEDLINE | ID: mdl-32879305

RESUMO

In this article, we adopt a radical approach for next generation ultra-low-power sensor design by embracing the evolutionary success of animals with extraordinary sensory information processing capabilities that allow them to survive in extreme and resource constrained environments. Stochastic resonance (SR) is one of those astounding phenomena, where noise, which is considered detrimental for electronic circuits and communication systems, plays a constructive role in the detection of weak signals. Here, we show SR in a photodetector based on monolayer MoS2 for detecting ultra-low-intensity subthreshold optical signals from a distant light emitting diode (LED). We demonstrate that weak periodic LED signals, which are otherwise undetectable, can be detected by a MoS2 photodetector in the presence of a finite and optimum amount of white Gaussian noise at a frugal energy expenditure of few tens of nano-Joules. The concept of SR is generic in nature and can be extended beyond photodetector to any other sensors.

8.
ACS Nano ; 14(11): 15440-15449, 2020 Nov 24.
Artigo em Inglês | MEDLINE | ID: mdl-33112615

RESUMO

Integration of low-power consumer electronics on glass can revolutionize the automotive and transport sectors, packaging industry, smart building and interior design, healthcare, life science engineering, display technologies, and many other applications. However, direct growth of high-performance, scalable, and reliable electronic materials on glass is difficult owing to low thermal budget. Similarly, development of energy-efficient electronic and optoelectronic devices on glass requires manufacturing innovations. Here, we accomplish both by relatively low-temperature (<600 °C) metal-organic chemical vapor deposition growth of atomically thin MoS2 on multicomponent glass and fabrication of low-power phototransistors using atomic layer deposition (ALD)-grown, high-k, and ultra-thin (∼20 nm) Al2O3 as the top-gate dielectric, circumventing the challenges associated with the ALD nucleation of oxides on inert basal planes of van der Waals materials. The MoS2 photodetectors demonstrate the ability to detect low-intensity visible light at high speed and low energy expenditure of ∼100 pico Joules. Furthermore, low device-to-device performance variation across the entire 1 cm2 substrate and aggressive channel length scalability confirm the technology readiness level of ultra-thin MoS2 photodetectors on glass.

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