Low-Noise Amplifier with Bypass for 5G New Radio Frequency n77 Band and n79 Band in Radio Frequency Silicon on Insulator Complementary Metal-Oxide Semiconductor Technology.

This paper presents the design of a low-noise amplifier (LNA) with a bypass mode for the n77/79 bands in 5G New Radio (NR). The proposed LNA integrates internal matching networks for both input and output, combining two LNAs for the n77 and n79 bands into a single chip. Additionally, a bypass mode is integrated to accommodate the flexible operation of the receiving system in response to varying input signal levels. For each frequency band, we designed a low-noise amplifier for the n77 band to expand the bandwidth to 900 MHz (3.3 GHz to 4.2 GHz) using resistive-capacitance (RC) feedback and series inductive-peaking techniques. For the n79 band, only the RC feedback technique was employed to optimize the performance of the LNA for its 600 MHz bandwidth (4.4 GHz to 5.0 GHz). Because wideband techniques can lead to a trade-off between gain and noise, causing potential degradation in noise performance, appropriate bandwidth design becomes crucial. The designed n77 band low-noise amplifier achieved a simulated gain of 22.6 dB and a noise figure of 1.7 dB. Similarly, the n79 band exhibited a gain of 21.1 dB and a noise figure of 1.5 dB with a current consumption of 10 mA at a 1.2 supply voltage. The bypass mode was designed with S21 of -3.7 dB and -5.0 dB for n77 and n79, respectively.

A Surface Acoustic Wave-Based PM 1.0 Fine Dust Detection System Using Full Digital Time-Interleaved Counters.

This paper proposed a fine dust detection system using time-interleaved counters in which surface acoustic wave (SAW) sensors changed the resonance point characteristic. When fine dust was applied to the SAW sensor, the resonance point decreased. The SAW oscillator made of the SAW sensor and radio frequency (RF) amplifier generated an oscillation frequency that was the same as the resonance frequency. The oscillation frequency was transferred to digital data by a 20-bit asynchronous counter. This system has two channels: a sensing channel and a reference channel. Each channel has a SAW oscillator and a 20-bit asynchronous counter. The difference of the two channel counter results is the frequency difference. Through this, it is possible to know whether fine dust adheres to the SAW sensor. The proposed circuit achieved 0.95 ppm frequency resolution when it was operated at a frequency of 460 MHz. This circuit was implemented in a TSMC 130 nm CMOS process.

RF-SOI Low-Noise Amplifier Using RC Feedback and Series Inductive-Peaking Techniques for 5G New Radio Application.

This paper presents a low-noise amplifier (LNA) with an integrated input and output matching network designed using RF-SOI technology. This LNA was designed with a resistive feedback topology and an inductive peaking technology to provide 600 MHz of bandwidth in the N79 band (4.4 GHz to 5.0 GHz). Generally, the resistive feedback structure used in broadband applications allows the input and output impedance to be made to satisfy the broadband conditions through low-impedance feedback. However, feedback impedance for excessive broadband characteristics can degrade the noise performance as a consequence. To achieve a better noise performance for a bandwidth of 600 MHz, the paper provided an optimized noise performance by selecting the feedback resistor value optimized for the N79 band. Additionally, an inductive peaking technique was applied to the designed low-noise amplifier to achieve a better optimized output matching network. The designed low-noise amplifier simulated a gain of 20.68 dB and 19.94 dB from 4.4 to 5.0 GHz, with noise figures of 1.57 dB and 1.73 dB, respectively. The input and output matching networks were also integrated, and the power consumption was designed to be 9.95 mA at a supply voltage of 1.2 V.

A Design of 10-Bit Asynchronous SAR ADC with an On-Chip Bandgap Reference Voltage Generator.

A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.

A Design of Adaptive Control and Communication Protocol for SWIPT System in 180 nm CMOS Process for Sensor Applications.

This paper presents an adaptive control and communication protocol (ACCP) for the ultra-low power simultaneous wireless information and power transfer (SWIPT) system for sensor applications. The SWIPT system-related operations depend on harvested radio frequency (RF) energy from the ambient environment. The necessary power for SWIPT system operation is not always available and it depends on the available RF energy in the ambient environment, transmitted RF power from the SWIPT transmitter, and the distance from the transmitter and channel conditions. Thus, an efficient control and communication protocol is required which can control the SWIPT system for sensor applications which mainly consists of a transmitter and a receiver. Multiple data frame structures are used to optimize the exchange of bits for the communication and control of the SWIPT system. Both SWIPT transmitter and receiver are capable of using multiple modulation schemes which can be switched depending on the channel condition and the available RF energy in the ambient environment. This provides support for automatic switching between the time switching scheme and power splitting scheme for the distribution of received RF power in the SWIPT receiver. It also adjusts the digital clock frequency at the SWIPT receiver according to the harvested power level to optimize the power consumption. The SWIPT receiver controller with ACCP is implemented in 180 nm CMOS technology. The RF frequency of the SWIPT operation is 5.8 GHz. Digital clock frequency at the SWIPT receiver can be adjusted between 32 kHz and 2 MHz which provides data rates from 8 to 500 kbps, respectively. The power consumption and area utilization are 12.3 µW and 0.81 mm².

A Highly Reliable, 5.8 GHz DSRC Wake-Up Receiver with an Intelligent Digital Controller for an ETC System.

In this article, a highly reliable radio frequency (RF) wake-up receiver (WuRx) is presented for electronic toll collection (ETC) applications. An intelligent digital controller (IDC) is proposed as the final stage for improving WuRx reliability and replacing complex analog blocks. With IDC, high reliability and accuracy are achieved by sensing and ensuring the successive, configurable number of wake-up signal cycles before enabling power-hungry RF transceiver. The IDC and range communication (RC) oscillator current consumption is reduced by a presented self-hibernation technique during the non-wake-up period. For accommodating wake-up signal frequency variation and enhancing WuRx accuracy, a digital hysteresis is incorporated. To avoid uncertain conditions during poor and false wake-up, a watch-dog timer for IDC self-recovery is integrated. During wake-up, the digital controller consumes 34.62 nW power and draws 38.47 nA current from a 0.9 V supply. In self-hibernation mode, its current reduces to 9.7 nA. It is fully synthesizable and needs 809 gates for its implementation in a 130 nm CMOS process with a 94 × 82 µm2 area. The WuRx measured power consumption is 2.48 µW, has -46 dBm sensitivity, and a 0.484 mm² chip area.

A Highly Accurate, Polynomial-Based Digital Temperature Compensation for Piezoresistive Pressure Sensor in 180 nm CMOS Technology.

Recently, piezoresistive-type (PRT) pressure sensors have been gaining attention in variety of applications due to their simplicity, low cost, miniature size and ruggedness. The electrical behavior of a pressure sensor is highly dependent on the temperature gradient which seriously degrades its reliability and reduces measurement accuracy. In this paper, polynomial-based adaptive digital temperature compensation is presented for automotive piezoresistive pressure sensor applications. The non-linear temperature dependency of a pressure sensor is accurately compensated for by incorporating opposite characteristics of the pressure sensor as a function of temperature. The compensation polynomial is fully implemented in a digital system and a scaling technique is introduced to enhance its accuracy. The resource sharing technique is adopted for minimizing controller area and power consumption. The negative temperature coefficient (NTC) instead of proportional to absolute temperature (PTAT) or complementary to absolute temperature (CTAT) is used as the temperature-sensing element since it offers the best temperature characteristics for grade 0 ambient temperature operating range according to the automotive electronics council (AEC) test qualification ACE-Q100. The shared structure approach uses an existing analog signal conditioning path, composed of a programmable gain amplifier (PGA) and an analog-to-digital converter (ADC). For improving the accuracy over wide range of temperature, a high-resolution sigma-delta ADC is integrated. The measured temperature compensation accuracy is within ±0.068% with full scale when temperature varies from -40 °C to 150 °C according to ACE-Q100. It takes 37 µs to compute the temperature compensation with a clock frequency of 10 MHz. The proposed technique is integrated in an automotive pressure sensor signal conditioning chip using a 180 nm complementary metal-oxide-semiconductor (CMOS) process.

A High Noise Immunity, 28 × 16-Channel Finger Touch Sensing IC Using OFDM and Frequency Translation Technique.

In this paper, a high noise immunity, 28 × 16-channel finger touch sensing IC for an orthogonal frequency division multiplexing (OFDM) touch sensing scheme is presented. In order to increase the signal-to-noise ratio (SNR), the OFDM sensing scheme is proposed. The transmitter (TX) transmits the orthogonal signal to each channels of the panel. The receiver (RX) detects the magnitude of the orthogonal frequency to be transmitted from the TX. Due to the orthogonal characteristics, it is robust to narrowband interference and noise. Therefore, the SNR can be improved. In order to reduce the noise effect of low frequencies, a mixer and high-pass filter are proposed as well. After the noise is filtered, the touch SNR attained is 60 dB, from 20 dB before the noise is filtered. The advantage of the proposed OFDM sensing scheme is its ability to detect channels of the panel simultaneously with the use of multiple carriers. To satisfy the linearity of the signal in the OFDM system, a high-linearity mixer and a rail-to-rail amplifier in the TX driver are designed. The proposed design is implemented in 90 nm CMOS process. The SNR is approximately 60 dB. The area is 13.6 mm², and the power consumption is 62.4 mW.

A Design of Small Area, 0.95 mW, 612⁻1152 MHz Open Loop Injection-Locked Frequency Multiplier for IoT Sensor Applications.

This paper presents a 612⁻1152 MHz Injection-Locked Frequency Multiplier (ILFM). The proposed ILFM is used to send an input signal to a receiver in only the I/Q mismatch calibration mode. Adopting a Phase-Locked Loop (PLL) to calibrate the receiver places a burden on this system because of the additional area and power consumption that is required. Instead of the PLL, to satisfy high-frequency, low-jitter and low-area requirements, a Ring Oscillator is adopted in the system. The free-running frequency of the ILFM is automatically and digitally calibrated to reflect the frequency of the injected signal from the harmonics of the reference clock. To control the frequency of the ILFM, the load current is digitally tuned with a 6-bit digital control signal. The proposed ILFM locks to the target frequency using a digitally controlled Frequency Locked Loop (FLL). This chip is fabricated using 1-poly 6-metal 0.18 µm CMOS and has achieved the wide tuning range of 612⁻1152 MHz. The power consumption is 0.95 mW from a supply voltage of 1.8 V. The measured phase noise of the ILFM is -108 dBc/Hz at a 1 MHz offset.