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This paper details the development and validation of a temperature sensing methodology using an un-trimmed oscillator-based integrated sensor implemented in the 0.18-µm SOI XFAB process, with a focus on thermal monitoring in system-on-chip (SoC) based DC-DC converters. Our study identifies a quadratic relationship between the oscillator output frequency and temperature, which forms the basis of our proposed calibration mechanism. This mechanism aims at mitigating process variation effects, enabling accurate temperature-to-frequency mapping. Our research proposes and characterizes several trimming-free calibration techniques, covering a spectrum from zero to thirty-one frequency-temperature measurement points. Notably, the Corrected One-Point calibration method, requiring only a single ambient temperature measurement, emerges as a practical solution that removes the need for a temperature chamber. This method, after adjustment, successfully reduces the maximum error to within ±2.95 °C. Additionally, the Two-Point calibration method demonstrates improved precision with a maximum positive error of +1.56 °C at -15 °C and a maximum negative error of -3.13 °C at +10 °C (R2 value of 0.9958). The Three-Point calibration method performed similarly, yielding an R2 value of 0.9956. The findings of this study indicate that competitive results in temperature sensor calibration can be achieved without circuit trimming, offering a viable alternative or a complementary approach to traditional trimming techniques.
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Modern applications of Internet of Things (IoT) devices require cheap and effective methods of measurement of physical quantities. Cheap IoT devices with sensor functionalities can detect a lack or excess of substances in everyday life or industry processes. One possible use of tension sensors in IoT applications is the automated replenishment process of fast moving consumer goods (FMCG) on shop shelves or home retail automation that allows for quick ordering of FMCG, where the IoT system is a part of smart packaging. For those reasons, a growing demand for cheap and tiny tension sensors has arisen. In this article, we propose a solution of a small flexible tension sensor fabricated in an amorphous InGaZnO (a-IGZO) thin-film process that can be integrated with other devices, e.g., near-field communications (NFC) or a barcode radio frequency identification (RFID) tag. The sensor was designed to magnify the slight internal changes in material properties caused by mechanical stress. These changes affect the dynamic electrical properties of specially designed inverters for a pair of ring oscillators, in which the frequencies become stress-dependent. In the article, we discuss and explain the approach to the optimum design of a ring oscillator that manifests the highest sensitivity to mechanical stress.
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Physically unclonable functions avoid storing secret information in non-volatile memories and only generate a key when it is necessary for an application, rising as a promising solution for the authentication of resource-constrained IoT devices. However, the need to minimize the predictability of physically unclonable functions is evident. The main purpose of this work is to determine the optimal way to construct a physically unclonable function. To do this, a ring oscillator physically unclonable function based on comparing oscillators in pairs has been implemented in an FPGA. This analysis shows that the frequencies of the oscillators greatly vary depending on their position in the FPGA, especially between oscillators implemented in different types of slices. Furthermore, the influence of the chosen locations of the ring oscillators on the quality of the physically unclonable function has been analyzed and we propose five strategies to select the locations of the oscillators. Among the strategies proposed, two of them stand out for their high uniqueness, reproducibility, and identifiability, so they can be used for authentication purposes. Finally, we have analyzed the reproducibility for the best strategy facing voltage and temperature variations, showing that it remains stable in the studied range.
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This paper proposes a high-precision LDO with low-temperature drift suitable for sensitive time-domain temperature sensors. Its topology is based on multiple feedback loops and a novel approach to frequency compensation, that allows the LDO to maintain a large DC gain while handling capacitive loads that vary over a wide range. The key design constraints are derived by using a simplified, yet intuitive and effective, small-signal analysis devised for LDOs with multiple feedback loops. Simulation and measurement results are presented for implementation in a standard 130 nm CMOS process: the LDO outputs a stable 1 V voltage, when the input voltage varies between 1.25 V to 1.5 V, the load current between 0 and 100 mA, and the load capacitor between zero and 400 pF. It exhibits a DC load regulation of 1 µV/mA, a 288 µV output offset with a standard deviation of 9.5 mV. A key feature for the envisaged application is the very low thermal drift of the output offset: only 14.4 mV across the temperature range of -40 °C to +150 °C. Overall, the LDO output voltage stays within +/-3.5% of the nominal DC value over the entire line voltage, load, and temperature ranges, without trimming. The LDO requires only 1.4µA quiescent current, yet it provides excellent responses to load transients. The output voltage undershoot and overshoot caused by the load current jumping between 0 and 100 mA in 1 µs are: 10%/22% for CL = 0 and 12%/16% for CL = 400 pF, respectively. A comparative analysis against seven LDOs published in the last decade, designed for similar levels of supply voltage and output voltage and current, shows that the LDO presented here is the best option for supplying sensitive time-domain temperature sensors. The smallest thermal drift of the output offset, smaller than +/-15 mV, that is, 6.7 times smaller than its closest competitor, and the best overall performance when PSR up to 1 kHz, was considered.
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Desenho de Equipamento , Retroalimentação , TemperaturaRESUMO
A ring oscillator is a well-known circuit used for generating random numbers, and interested readers can find many research results concerning the evaluation of the randomness with a packaged test suit. However, the authors think there is room for evaluating the unpredictability of a sequence from another viewpoint. In this paper, the authors focus on Wold's RO-based generator and propose a statistical test to numerically evaluate the randomness of the RO-based generator. The test adopts the state transition probabilities in a Markov process and is designed to check the uniformity of the probabilities based on hypothesis testing. As a result, it is found that the RO-based generator yields a biased output from the viewpoint of the transition probability if the number of ROs is small. More precisely, the transitions 01â01 and 11â11 happen frequently when the number l of ROs is less than or equal to 10. In this sense, l>10 is recommended for use in any application, though a packaged test suit is passed. Thus, the authors believe that the proposed test contributes to evaluating the unpredictability of a sequence when used together with available statistical test suits, such as NIST SP800-22.
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This article introduces a new class of physical unclonable functions (PUFs) based on the Fibonacci ring oscillator (FIRO). The research conducted here proves that before reaching the desired randomness, the oscillator shows a certain degree of repeatability and uniqueness in the initial sequence of internal state transitions. The use of an FIRO in conjunction with the restart method makes it possible to obtain a set of short boot sequences, which are processed with an innovative feature extraction algorithm that enables reliable device identification. This approach ensures the reuse of the existing random number generator (RNG), rather than multiplying ring oscillators in a dedicated structure. Moreover, the algorithm for the recovery of the device key from the boot set can be successfully implemented in the authorizing center, thus significantly releasing the resources of authorized low-complexity devices. The proposed methodology provides an easily obtainable key with identifiability, which was proven experimentally on FPGAs from different manufacturers.
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AlgoritmosRESUMO
Field-effect transistor (FET)-based biosensors have garnered significant attention for their label-free electrical detection of charged biomolecules. Whereas conventional output parameters such as threshold voltage and channel current have been widely used for the detection and quantitation of analytes of interest, they require bulky instruments and specialized readout circuits, which often limit point-of-care testing applications. In this study, we demonstrate a simple conversion method that transforms the surface potential into an oscillating signal as an output of the FET-based biosensor. The oscillation frequency is proposed as a parameter for FET-based biosensors owing to its intrinsic advantages of simple and compact implementation of readout circuits as well as high compatibility with neuromorphic applications. An extended-gate biosensor comprising an Al2O3-deposited sensing electrode and a readout transistor is connected to a ring oscillator that generates surface potential-controlled oscillation for pH sensing. Electrical measurement of the oscillation frequency as a function of pH reveals that the oscillation frequency can be used as a sensitive and reliable output parameter in FET-based biosensors for the detection of chemical and biological species. We confirmed that the oscillation frequency is directly correlated with the threshold voltage. For signal amplification, the effects of circuit parameters on pH sensitivity are investigated using different methods, including electrical measurements, analytical calculations, and circuit simulations. An Arduino board to measure the oscillation frequency is integrated with the proposed sensor to enable portable and real-time pH measurement for point-of-care testing applications.
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Técnicas Biossensoriais , Eletrodos , Transistores EletrônicosRESUMO
A cloud service to offer entropy has been paid much attention to. As one of the entropy sources, a physical random number generator is used as a true random number generator, relying on its irreproducibility. This paper focuses on a physical random number generator using a field-programmable gate array as an entropy source by employing ring oscillator circuits as a representative true random number generator. This paper investigates the effects of an XOR gate in the oscillation circuit by observing the output signal period. It aims to reveal the relationship between inputs and the output through the XOR gate in the target generator. The authors conduct two experiments to consider the relevance. It is confirmed that combining two ring oscillators with an XOR gate increases the complexity of the output cycle. In addition, verification using state transitions showed that the probability of the state transitions was evenly distributed by increasing the number of ring oscillator circuits.
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This work presented a comparison between two Voltage Controlled Oscillators (VCOs) designed in 65 nm CMOS technology. The first architecture based on a Ring Oscillator (RO) was designed using three Current Mode Logic (CML) stages connected in a loop, while the second one was based on an LC-tank resonator. This analysis aimed to choose a VCO architecture able to be integrated into a rad-hard Phase Locked Loop. It had to meet the requirements of the SpaceFibre protocol, which supports frequencies up to 6.25 GHz, for space applications. The full custom schematic and layout designs are shown, and Single Event Effect simulations results, performed with a double exponential current pulses generator, are presented in detail for both VCOs. Although the RO-VCO performances in terms of technology scaling and high-integration density were attractive, the simulations on the process variations demonstrated its inability to generate the target frequency in harsh operating conditions. Instead, the LC-VCO highlighted a lower influence through Process-Voltage-Temperature simulations on the oscillation frequency. Both architectures were biased with a supply voltage of 1.2 V. The achieved results for the second architecture analyzed were attractive to address the requirements of the new SpaceFibre aerospace standard.
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We propose a ring oscillator (RO) based current-to-voltage-to-frequency (I-V-F) converting current transducer with a cascade bias circuit. The I-V-F converting scheme guarantees highly stable biasing against RO, with a rail-to-rail output operation. This device was fabricated using National NanoFab Center (NNFC) 180 nm complementary metal-oxide-semiconductor (CMOS) technology, which achieves a current resolution of 1 nA in a measurement range up to 200 nA. A noise floor of 11.8 pA/âHz, maximum differential nonlinearity (DNL) of 0.15 in 1 nA steps, and rail-to-rail output with a 1.8 V power supply is achieved. The proposed transducer can be effectively applied to bio-sensing devices requiring a compact area and low power consumption with a low current output. The fabricated structure can be applied to monolithic-three-dimensional integration with a bio-sensing device.
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A ring oscillator is a system in which one species regulates the next, which regulates the next and so on until the last species regulates the first. In addition, the number of the regulations which are negative, and so result in a reduction in the regulated species, is odd, making the overall feedback in the loop negative. In ring oscillators, the probability of oscillations is maximised if the degradation rates of the species are equal. When there is more than one loop in the regulatory network, the dynamics can be more complicated. Here, a systematic way of organising the characteristic equation of ODE models of regulatory networks is provided. This facilitates the identification of Hopf bifurcations. It is shown that the probability of oscillations in non-ring systems is maximised for unequal degradation rates. For example, when there is a ring and a second ring employing a subset of the genes in the first ring, then the probability of oscillations is maximised when the species in the sub-ring degrade more slowly than those outside, for a negative feedback subring. When the sub-ring forms a positive feedback loop, the optimal degradation rates are larger for the species in the sub-ring, provided the positive feedback is not too strong. By contrast, optimal degradation rates are smaller for the species in the sub-ring, when the positive feedback is very strong. Adding a positive feedback loop to a repressilator increases the probability of oscillations, provided the positive feedback is not too strong, whereas adding a negative feedback loop decreases the probability of oscillations. The work is illustrated with numerical simulations of example systems: an autoregulatory gene model in which transcription is downregulated by the protein dimer and three-species and four-species gene regulatory network examples.
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Relógios Biológicos , Simulação por Computador , Redes Reguladoras de Genes , Modelos GenéticosRESUMO
This paper demonstrates an on-chip electrical cold-start technique to achieve low-voltage and fast start up of a boost converter for autonomous thermal energy harvesting from human body heat. An improved charge transfer through high gate-boosted switches by means of cross-coupled complementary charge pumps enables voltage multiplication of the low input voltage during cold start. The start-up voltage multiplier operates with an on-chip clock generated by an ultra-low-voltage ring oscillator. The proposed cold-start scheme implemented in a general purpose 0.18µm CMOS process assists an inductive boost converter to start operation with a minimum input voltage of 57mV in 135 ms while consuming only 90 nJ of energy from the harvesting source, without using additional sources of energy or additional off-chip components.
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The paper presents a novel dual-band six-phase voltage-control oscillator. The voltage-controlled oscillator (VCO) with a single-ended delay cell architecture has a lower power consumption, a smaller chip area, and a larger output swing than one with a differential delay cell architecture. However, the conventional even-phase outputs ring-type VCO cannot be implemented using single-ended delay cells. In other words, the VCO with single-ended delay cells meets most of the requirements of a sensor circuit system, except even-phase outputs function. This work presents a dual-band six-phase ring type VCO, which is implemented using the proposed single-ended delay cell. The proposed VCO both exhibits the advantages of single-ended delay cells and differential delay cells. The proposed delay cell has a band-switching function, which improves the jitter performance of a VCO in which it is used. The proposed VCO can be operated at 890â»1080 MHz. The peak-to-peak jitter and the root mean square jitter are the 35.5 ps and 2.8 ps (at 1 GHz), respectively. The maximal power consumption is approximately 6.4 mW at a supply voltage of 1.8 V in a United Microelectronics Corporation 0.18 µm RF CMOS process. The area of the chip is 0.195 × 0.208 mm².
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Direct time-of-flight (dTOF) image sensors require accurate and robust timing references for precise depth calculation. On-chip timing references are well-known and understood, but for imaging systems where several thousands of pixels require seamless references, area and power consumption limit the use of more traditional synthesizers, such as phase/delay-locked loops (PLLs/DLLs). Other methods, such as relative timing measurement (start/stop), require constant foreground calibration, which is not feasible for outdoor applications, where conditions of temperature, background illumination, etc. can change drastically and frequently. In this paper, a scalable reference generation and synchronization is provided, using minimum resources of area and power, while being robust to mismatches. The suitability of this approach is demonstrated through the design of an 8 × 8 time-to-digital converter (TDC) array, distributed over 1.69 mm², fabricated using TSMC 65 nm technology (1.2 V core voltage and 4 metal layers-3 thin + 1 thick). Each TDC is based on a ring oscillator (RO) coupled to a ripple counter, occupying a very small area of 550 µ m², while consuming 500 µ W of power, and has 2 µ s range, 125 ps least significant bit (LSB), and 14-bit resolution. Phase and frequency locking among the ROs is achieved, while providing 18 dB phase noise improvement over an equivalent individual oscillator. The integrated root mean square (RMS) jitter is less than 9 ps, the instantaneous frequency variation is less than 0.11%, differential nonlinearity (DNL) is less than 2 LSB, and integral nonlinearity (INL) is less than 3 LSB.
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A complementary metal-oxide-semiconductor (CMOS) chip biosensor was developed for cell viability monitoring based on an array of capacitance sensors utilizing a ring oscillator. The chip was packaged in a low temperature co-fired ceramic (LTCC) module with a flip chip bonding technique. A microcontroller operates the chip, while the whole measurement system was controlled by PC. The developed biosensor was applied for measurement of the proliferation stage of adherent cells where the sensor response depends on the ratio between healthy, viable and multiplying cells, which adhere onto the chip surface, and necrotic or apoptotic cells, which detach from the chip surface. This change in cellular adhesion caused a change in the effective permittivity in the vicinity of the sensor element, which was sensed as a change in oscillation frequency of the ring oscillator. The sensor was tested with human lung epithelial cells (BEAS-2B) during cell addition, proliferation and migration, and finally detachment induced by trypsin protease treatment. The difference in sensor response with and without cells was measured as a frequency shift in the scale of 1.1 MHz from the base frequency of 57.2 MHz. Moreover, the number of cells in the sensor vicinity was directly proportional to the frequency shift.
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Técnicas Biossensoriais/métodos , Proliferação de Células/fisiologia , Linhagem Celular , Sobrevivência Celular/fisiologia , Temperatura Baixa , HumanosRESUMO
Authentication is a crucial security service for the wireless sensor networks (WSNs) in versatile domains. The deployment of WSN devices in the untrusted open environment and the resource-constrained nature make the on-chip authentication an open challenge. The strong physical unclonable function (PUF) came in handy as light-weight authentication security primitive. In this paper, we present the first ring oscillator (RO) based strong physical unclonable function (PUF) with high resilience to both the electromagnetic (EM) side-channel attack and the support vector machine (SVM) modelling attack. By employing an RO based PUF architecture with the current starved inverter as the delay cell, the oscillation power is significantly reduced to minimize the emitted EM signal, leading to greatly enhanced immunity to the EM side-channel analysis attack. In addition, featuring superior reconfigurability due to the conspicuously simplified circuitries, the proposed implementation is capable of withstanding the SVM modelling attack by generating and comparing a large number of RO frequency pairs. The reported experimental results validate the prototype of a 9-stage RO PUF fabricated using standard 65 nm complementary-metal-oxide-semiconductor (CMOS) process. Operating at the supply voltage of 1.2 V and the frequency of 100 KHz, the fabricated RO PUF occupies a compact silicon area of 250 µ m 2 and consumes a power as low as 5.16 µ W per challenge-response pair (CRP). Furthermore, the uniqueness and the worst-case reliability are measured to be 50.17% and 98.30% for the working temperature range of -40â¼120 ∘ C and the supply voltage variation of ±2%, respectively. Thus, the proposed PUF is applicable for the low power, low cost and secure WSN communications.
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The effects of ionizing radiation on field-programmable gate arrays (FPGAs) have been investigated in depth during the last decades. The impact of these effects is typically evaluated on implementations which have a deterministic behavior. In this article, two well-known true-random number generators (TRNGs) based on sampling jittery signals have been exposed to a Co-60 radiation source as in the standard tests for space conditions. The effects of the accumulated dose on these TRNGs, an in particular, its repercussion over their randomness quality (e.g., entropy or linear complexity), have been evaluated by using two National Institute of Standards and Technology (NIST) statistical test suites. The obtained results clearly show how the degradation of the statistical properties of these TRNGs increases with the accumulated dose. It is also notable that the deterioration of the TRNG (non-deterministic component) appears before that the degradation of the deterministic elements in the FPGA, which compromises the integrated circuit lifetime.
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Random Telegraph Noise (RTN) is one of the major reliability concerns in nanoscale complementary metal-oxide semiconductor (CMOS) technologies. In this paper, we discuss the characterization of RTN in 40â¯nm CMOS technology using Ring Oscillators (ROSCs). We used different types of ROSCs to study the temporal and spectral characteristics of the RTN. We conducted measurements on one of the arrays with 128 identical ROSC cells. These results enabled statistical characterization of the RTN amplitude strength and its frequency characteristics in different supply voltage variations from 0.5â¯V to 0.7â¯V. At power supply of 0.65â¯V, dominant and observable RTN amplitude above 0.37% Δf/fmean is found in 60% of cells in the array. Further, the capture and emission time constant τe//c can be extracted from the measurements, the values observed ranging from 0.2⯵s to 10â¯ms.
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The reliability and durability of integrated circuits (ICs), present in almost every electronic system, from consumer electronics to the automotive or aerospace industries, have been and will continue to be critical concerns for IC chip makers, especially in scaled nanometer technologies. In this context, ICs are expected to deliver optimal performance and reliability throughout their projected lifetime. However, real-time reliability assessment and remaining lifetime projections during in-field IC operation remain unknown due to the absence of trustworthy on-chip reliability monitors. The integration of such on-chip monitors has recently gained significant importance because they can provide real-time IC reliability extraction by exploiting the fundamental physics of two of the major reliability degradation phenomena: bias temperature instability (BTI) and hot carrier degradation (HCD). In this work, we present an extensive study of ring oscillator (RO)-based degradation and annealing monitors designed on our latest 28 nm versatile array chip. This test vehicle, along with a dedicated test setup, enabled the reliable statistical characterization of BTI- and HCD-stressed as well as annealed RO monitor circuits. The versatility of the test vehicle presented in this work permits the execution of accelerated degradation tests together with annealing experiments conducted on RO-based reliability monitor circuits. From these experiments, we have constructed precise annealing maps that provide detailed insights into the annealing behavior of our monitors as a function of temperature and time, ultimately revealing the usage history of the IC.
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The electro-thermal performance of silicon nanosheet field-effect transistors (NSFETs) with various parasitic bottom transistor (trpbt)-controlling schemes is evaluated. Conventional punch-through stopper, trench inner-spacer (TIS), and bottom oxide (BOX) schemes were investigated from single-device to circuit-level evaluations to avoid overestimating heat's impact on performance. For single-device evaluations, the TIS scheme maintains the device temperature 59.6 and 50.4 K lower than the BOX scheme for n/pFETs, respectively, due to the low thermal conductivity of BOX. However, when the over-etched S/D recess depth (TSD) exceeds 2 nm in the TIS scheme, the RC delay becomes larger than that of the BOX scheme due to increased gate capacitance (Cgg) as the TSD increases. A higher TIS height prevents the Cgg increase and exhibits the best electro-thermal performance at single-device operation. Circuit-level evaluations are conducted with ring oscillators using 3D mixed-mode simulation. Although TIS and BOX schemes have similar oscillation frequencies, the TIS scheme has a slightly lower device temperature. This thermal superiority of the TIS scheme becomes more pronounced as the load capacitance (CL) increases. As CL increases from 1 to 10 fF, the temperature difference between TIS and BOX schemes widens from 1.5 to 4.8 K. Therefore, the TIS scheme is most suitable for controlling trpbt and improving electro-thermal performance in sub-3 nm node NSFETs.