Simulation for Electrical Performances of the Capacitorless Dynamic Random Access Memory Based on Junctionless FinFETs.

This paper report a junctionless fin-type field-effect-transistor based capacitorless dynamic random access memory using three-dimensional technology computer-aided design simulations. The proposed 1T-DRAM is made up of a silicon germanium storage region surrounding a silicon fin. When the two materials form a heterojunction, a potential well is formed by the band discontinuity which carriers can be stored. During the program operation, band-to-band tunneling and gate-induced drain leakage occur simultaneously due to the gate and drain bias. Because of these phenomena, the electron-hole pair occurs, and generated holes are stored in the storage region by potential well. The holes formed are positively charged within the storage region, which mitigates the depletion of the channel and improves the operating current. The proposed device realizes the memory operation by the difference of the operating current depending on the presence or absence of the stored holes. In this work, the device is analyzed and optimized in detail. The proposed 1T-DRAM shows excellent performance with a retention time of 161 ms based on 50% of the maximum data margin.