Low Latency TOE with Double-Queue Structure for 10Gbps Ethernet on FPGA.

Yang, Dan; Xu, Xuhan; Chen, Tianyang; Chen, Yanhao; Zhang, Junjie

Yang, Dan; Xu, Xuhan; Chen, Tianyang; Chen, Yanhao; Zhang, Junjie.

Afiliação

Yang D; Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai Institute for Advanced Communication and Data Science, Shanghai University, Shanghai 200072, China.
Xu X; Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai Institute for Advanced Communication and Data Science, Shanghai University, Shanghai 200072, China.
Chen T; Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai Institute for Advanced Communication and Data Science, Shanghai University, Shanghai 200072, China.
Chen Y; Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai Institute for Advanced Communication and Data Science, Shanghai University, Shanghai 200072, China.
Zhang J; Key Laboratory of Specialty Fiber Optics and Optical Access Networks, Shanghai Institute for Advanced Communication and Data Science, Shanghai University, Shanghai 200072, China.

Sensors (Basel) ; 23(10)2023 May 12.

Article em En | MEDLINE | ID: mdl-37430603

Palavras-chave

FPGA; TCP/IP offload engine; low latency; model analysis; network traffic

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Texto completo: 1 Bases de dados: MEDLINE Idioma: En Revista: Sensors (Basel) Ano de publicação: 2023 Tipo de documento: Article País de afiliação: China