ABSTRACT
Two-dimensional-material-based memristors are emerging as promising enablers of new computing systems beyond von Neumann computers. However, the most studied anion-vacancy-enabled transition metal dichalcogenide memristors show many undesirable performances, e.g., high leakage currents, limited memory windows, high programming currents, and limited endurance. Here, we demonstrate that the emergent van der Waals metal phosphorus trisulfides with unconventional nondefective vacancy provide a promising paradigm for high-performance memristors. The different vacancy types (i.e., defective and nondefective vacancies) induced memristive discrepancies are uncovered. The nondefective vacancies can provide an ultralow diffusion barrier and good memristive structure stability giving rise to many desirable memristive performances, including high off-state resistance of 1012 Ω, pA-level programming currents, large memory window up to 109, more than 7-bit conductance states, and good endurance. Furthermore, a high-yield (94%) memristor crossbar array is fabricated and implements multiple image processing successfully, manifesting the potential for in-memory computing hardware.
ABSTRACT
Physical implementations of reservoir computing (RC) based on the emerging memristors have become promising candidates of unconventional computing paradigms. Traditionally, sequential approaches by time-multiplexing volatile memristors have been prevalent because of their low hardware overhead. However, they suffer from the problem of speed degradation and fall short of capturing the spatial relationship between the time-domain inputs. Here, we explore a new avenue for RC using memristor crossbar arrays with device-to-device variations, which serve as physical random weight matrices of the reservoir layers, enabling faster computation thanks to the parallelism of matrix-vector multiplication as an intensive operation in RC. To achieve this new RC architecture, ultralow-current, self-selective memristors are fabricated and integrated without the need of transistors, showing greater potential of high scalability and three-dimensional integrability compared to the previous realizations. The information processing ability of our RC system is demonstrated in asks of recognizing digit images and waveforms. This work indicates that the 'nonidealities' of the emerging memristor devices and circuits are a useful source of inspiration for new computing paradigms.
ABSTRACT
With the booming growth of artificial intelligence (AI), the traditional von Neumann computing architecture based on complementary metal oxide semiconductor devices are facing memory wall and power wall. Memristor based in-memory computing can potentially overcome the current bottleneck of computer and achieve hardware breakthrough. In this review, the recent progress of memory devices in material and structure design, device performance and applications are summarized. Various resistive switching materials, including electrodes, binary oxides, perovskites, organics, and two-dimensional materials, are presented and their role in the memristor are discussed. Subsequently, the construction of shaped electrodes, the design of functional layer and other factors influencing the device performance are analyzed. We focus on the modulation of the resistances and the effective methods to enhance the performance. Furthermore, synaptic plasticity, optical-electrical properties, the fashionable applications in logic operation and analog calculation are introduced. Finally, some critical issues such as the resistive switching mechanism, multi-sensory fusion, system-level optimization are discussed.
ABSTRACT
2D materials with intriguing properties have been widely used in optoelectronics. However, electronic devices suffered from structural damage due to the ultrathin materials and uncontrolled defects at interfaces upon metallization, which hindered the development of reliable devices. Here, a damage-free Au/h-BN/Au memristor is reported using a clean, water-assisted metal transfer approach by physically assembling Au electrodes onto the layered h-BN which minimized the structural damage and undesired interfacial defects. The memristors demonstrate significantly improved performance with the coexistence of nonpolar and threshold switching as well as tunable current levels by controlling the compliance current, compared with devices with evaporated contacts. The devices integrated into an array show suppressed sneak path current and can work as both logic gates and latches to implement logic operations allowing in-memory computing. Cross-sectional scanning transmission electron microscopy analysis validates the feasibility of this nondestructive metal integration approach, the crucial role of high-quality atomically sharp interface in resistive switching, and a direct observation of percolation path. The underlying mechanism of boron vacancies-assisted transport is further supported experimentally by conductive atomic force microscopy free from process-induced damage, and theoretically by ab initio simulations.
ABSTRACT
Conventional digital computers can execute advanced operations by a sequence of elementary Boolean functions of 2 or more bits. As a result, complicated tasks such as solving a linear system or solving a differential equation require a large number of computing steps and an extensive use of memory units to store individual bits. To accelerate the execution of such advanced tasks, in-memory computing with resistive memories provides a promising avenue, thanks to analog data storage and physical computation in the memory. Here, we show that a cross-point array of resistive memory devices can directly solve a system of linear equations, or find the matrix eigenvectors. These operations are completed in just one single step, thanks to the physical computing with Ohm's and Kirchhoff's laws, and thanks to the negative feedback connection in the cross-point circuit. Algebraic problems are demonstrated in hardware and applied to classical computing tasks, such as ranking webpages and solving the Schrödinger equation in one step.
ABSTRACT
Two-dimensional materials have been widely used in electronics due to their electrical properties that are not accessible in traditional materials. Here, we present the first demonstration of logic functions of unipolar memristors made of functionalized HfSe2-xOx flakes and memtransistors made of MoS2/graphene/HfSe2-xOx van der Waals heterostructures. The two-terminal memristors exhibit stable unipolar switching behavior with high switching ratio (>106), high operating temperature (106 °C), long-term endurance (>104 s), and multibit data storage and can operate as memory latches and logic gates. Benefiting from these superior memristive properties, the three-terminal heterostructure memtransistors show wide tunability in electrical switching behaviors, which can simultaneously implement logic operation and data storage. Finally, we investigate their application prospect in logical units with memory capability, such as D-type flip-flop. These results demonstrate the potential of two-dimensional materials for resistive switching applications and open up an avenue for future in-memory computing.
ABSTRACT
Electronic textiles may revolutionize many fields, such as communication, health care and artificial intelligence. To date, unfortunately, computing with them is not yet possible. Memristors are compatible with the interwoven structure and manufacturing process in textiles because of its two-terminal crossbar configuration. However, it remains a challenge to realize textile memristors owing to the difficulties in designing advanced memristive materials and achieving high-quality active layers on fiber electrodes. Herein we report a robust textile memristor based on an electrophoretic-deposited active layer of deoxyribonucleic acid (DNA) on fiber electrodes. The unique architecture and orientation of DNA molecules with the incorporation of Ag nanoparticles offer the best-in-class performances, e.g., both ultra-low operation voltage of 0.3â V and power consumption of 100â pW and high switching speed of 20â ns. Fundamental logic calculations such as implication and NAND are demonstrated as functions of textile chips, and it has been thus integrated with power-supplying and light emitting modules to demonstrate an all-fabric information processing system.
ABSTRACT
Road transportation is the backbone of modern economies, albeit it annually costs 1.25 million deaths and trillions of dollars to the global economy, and damages public health and the environment. Deep learning is among the leading-edge methods used for transportation-related predictions, however, the existing works are in their infancy, and fall short in multiple respects, including the use of datasets with limited sizes and scopes, and insufficient depth of the deep learning studies. This paper provides a novel and comprehensive approach toward large-scale, faster, and real-time traffic prediction by bringing four complementary cutting-edge technologies together: big data, deep learning, in-memory computing, and Graphics Processing Units (GPUs). We trained deep networks using over 11 years of data provided by the California Department of Transportation (Caltrans), the largest dataset that has been used in deep learning studies. Several combinations of the input attributes of the data along with various network configurations of the deep learning models were investigated for training and prediction purposes. The use of the pre-trained model for real-time prediction was explored. The paper contributes novel deep learning models, algorithms, implementation, analytics methodology, and software tool for smart cities, big data, high performance computing, and their convergence.
ABSTRACT
The semiconductor industry is currently challenged by the emergence of Internet of Things, Big data, and deep-learning techniques to enable object recognition and inference in portable computers. These revolutions demand new technologies for memory and computation going beyond the standard CMOS-based platform. In this scenario, resistive switching memory (RRAM) is extremely promising in the frame of storage technology, memory devices, and in-memory computing circuits, such as memristive logic or neuromorphic machines. To serve as enabling technology for these new fields, however, there is still a lack of industrial tools to predict the device behavior under certain operation schemes and to allow for optimization of the device properties based on materials and stack engineering. This work provides an overview of modeling approaches for RRAM simulation, at the level of technology computer aided design and high-level compact models for circuit simulations. Finite element method modeling, kinetic Monte Carlo models, and physics-based analytical models will be reviewed. The adaptation of modeling schemes to various RRAM concepts, such as filamentary switching and interface switching, will be discussed. Finally, application cases of compact modeling to simulate simple RRAM circuits for computing will be shown.
ABSTRACT
Ferroelectrics have great potential in the field of nonvolatile memory due to programmable polarization states by external electric field in nonvolatile manner. However, complementary metal oxide semiconductor compatibility and uniformity of ferroelectric performance after size scaling have always been two thorny issues hindering practical application of ferroelectric memory devices. The emerging ferroelectricity of wurtzite structure nitride offers opportunities to circumvent the dilemma. This review covers the mechanism of ferroelectricity and domain dynamics in ferroelectric AlScN films. The performance optimization of AlScN films grown by different techniques is summarized and their applications for memories and emerging in-memory computing are illustrated. Finally, the challenges and perspectives regarding the commercial avenue of ferroelectric AlScN are discussed.
ABSTRACT
This article proposes a novel design for an in-memory computing SRAM, the DAM SRAM CORE, which integrates storage and computational functionality within a unified 11T SRAM cell and enables the performance of large-scale parallel Multiply-Accumulate (MAC) operations within the SRAM array. This design not only improves the area efficiency of the individual cells but also realizes a compact layout. A key highlight of this design is its employment of a dynamic aXNOR-based computation mode, which significantly reduces the consumption of both dynamic and static power during the computational process within the array. Additionally, the design innovatively incorporates a self-stabilizing voltage gradient quantization circuit, which enhances the computational accuracy of the overall system. The 64 × 64 bit DAM SRAM CORE in-memory computing core was fabricated using the 55 nm CMOS logic process and validated via simulations. The experimental results show that this core can deliver 5-bit output results with 1-bit input feature data and 1-bit weight data, while maintaining a static power consumption of 0.48 mW/mm2 and a computational power consumption of 11.367 mW/mm2. This showcases its excellent low-power characteristics. Furthermore, the core achieves a data throughput of 109.75 GOPS and exhibits an impressive energy efficiency of 21.95 TOPS/W, which robustly validate the effectiveness and advanced nature of the proposed in-memory computing core design.
ABSTRACT
Neural networks are increasingly used to solve optimization problems in various fields, including operations research, design automation, and gene sequencing. However, these networks face challenges due to the nondeterministic polynomial time (NP)-hard issue, which results in exponentially increasing computational complexity as the problem size grows. Conventional digital hardware struggles with the von Neumann bottleneck, the slowdown of Moore's law, and the complexity arising from heterogeneous system design. Two-dimensional (2D) memristors offer a potential solution to these hardware challenges, with their in-memory computing, decent scalability, and rich dynamic behaviors. In this study, we explore the use of nonvolatile 2D memristors to emulate synapses in a discrete-time Hopfield neural network, enabling the network to solve continuous optimization problems, like finding the minimum value of a quadratic polynomial, and tackle combinatorial optimization problems like Max-Cut. Additionally, we coupled volatile memristor-based oscillators with nonvolatile memristor synapses to create an oscillatory neural network-based Ising machine, a continuous-time analog dynamic system capable of solving combinatorial optimization problems including Max-Cut and map coloring through phase synchronization. Our findings demonstrate that 2D memristors have the potential to significantly enhance the efficiency, compactness, and homogeneity of integrated Ising machines, which is useful for future advances in neural networks for optimization problems.
ABSTRACT
The conventional computing architecture faces substantial challenges, including high latency and energy consumption between memory and processing units. In response, in-memory computing has emerged as a promising alternative architecture, enabling computing operations within memory arrays to overcome these limitations. Memristive devices have gained significant attention as key components for in-memory computing due to their high-density arrays, rapid response times, and ability to emulate biological synapses. Among these devices, two-dimensional (2D) material-based memristor and memtransistor arrays have emerged as particularly promising candidates for next-generation in-memory computing, thanks to their exceptional performance driven by the unique properties of 2D materials, such as layered structures, mechanical flexibility, and the capability to form heterojunctions. This review delves into the state-of-the-art research on 2D material-based memristive arrays, encompassing critical aspects such as material selection, device performance metrics, array structures, and potential applications. Furthermore, it provides a comprehensive overview of the current challenges and limitations associated with these arrays, along with potential solutions. The primary objective of this review is to serve as a significant milestone in realizing next-generation in-memory computing utilizing 2D materials and bridge the gap from single-device characterization to array-level and system-level implementations of neuromorphic computing, leveraging the potential of 2D material-based memristive devices.
ABSTRACT
Costly data movement in terms of time and energy in traditional von Neumann systems is exacerbated by emerging information technologies related to artificial intelligence. In-memory computing (IMC) architecture aims to address this problem. Although the IMC hardware prototype represented by a memristor is developed rapidly and performs well, the sneak path issue is a critical and unavoidable challenge prevalent in large-scale and high-density crossbar arrays, particularly in three-dimensional (3D) integration. As a perfect solution to the sneak-path issue, a self-rectifying memristor (SRM) is proposed for 3D integration because of its superior integration density. To date, SRMs have performed well in terms of power consumption (aJ level) and scalability (>102 Mbit). Moreover, SRM-configured 3D integration is considered an ideal hardware platform for 3D IMC. This review focuses on the progress in SRMs and their applications in 3D memory, IMC, neuromorphic computing, and hardware security. The advantages, disadvantages, and optimization strategies of SRMs in diverse application scenarios are illustrated. Challenges posed by physical mechanisms, fabrication processes, and peripheral circuits, as well as potential solutions at the device and system levels, are also discussed.
ABSTRACT
Ternary content-addressable memory (TCAM) is promising for data-intensive artificial intelligence applications due to its large-scale parallel in-memory computing capabilities. However, it is still challenging to build a reliable TCAM cell from a single circuit component. Here, we demonstrate a single transistor TCAM based on a floating-gate two-dimensional (2D) ambipolar MoTe2 field-effect transistor with graphene contacts. Our bottom graphene contacts scheme enables gate modulation of the contact Schottky barrier heights, facilitating carrier injection for both electrons and holes. The 2D nature of our channel and contact materials provides device scaling potentials beyond silicon. By integration with a floating-gate stack, a highly reliable nonvolatile memory is achieved. Our TCAM cell exhibits a resistance ratio larger than 1000 and symmetrical complementary states, allowing the implementation of large-scale TCAM arrays. Finally, we show through circuit simulations that in-memory Hamming distance computation is readily achievable based on our TCAM with array sizes up to 128 cells.
ABSTRACT
As a promising alternative to the von Neumann architecture, in-memory computing holds the promise of delivering a high computing capacity while consuming low power. In this paper, we show that the ferroelectric reconfigurable transistor can serve as a versatile logic-in-memory unit that can perform logic operations and data storage concurrently. When functioning as memory, a ferroelectric reconfigurable transistor can implement content-addressable memory (CAM) with a 1-transistor-per-bit density. With the switchable polarity of the ferroelectric reconfigurable transistor, XOR/XNOR-like matching operation in CAM is realized in a single transistor, which can offer a significant improvement in area and energy efficiency compared to conventional CAMs. NAND- and NOR-arrays of CAMs are also demonstrated, which enable multibit matching in a single reading operation. In addition, the NOR array of CAM cells effectively measures the Hamming distance between the input query and the stored entries. When functioning as a logic element, a ferroelectric reconfigurable transistor can be switched between n- and p-type modes. Utilizing the switchable polarity of these ferroelectric Schottky barrier transistors, we demonstrate reconfigurable logic gates with NAND/NOR dual functions, whose input-output mapping can be transformed in real time without changing the layout, and the configuration is nonvolatile.
ABSTRACT
Artificial neural networks (ANNs), inspired by the human brain's network of neurons and synapses, enable computing machines and systems to execute cognitive tasks, thus embodying artificial intelligence (AI). Since the performance of ANNs generally improves with the expansion of the network size, and also most of the computation time is spent for matrix operations, AI computation have been performed not only using the general-purpose central processing unit (CPU) but also architectures that facilitate parallel computation, such as graphic processing units (GPUs) and custom-designed application-specific integrated circuits (ASICs). Nevertheless, the substantial energy consumption stemming from frequent data transfers between processing units and memory has remained a persistent challenge. In response, a novel approach has emerged: an in-memory computing architecture harnessing analog memory elements. This innovation promises a notable advancement in energy efficiency. The core of this analog AI hardware accelerator lies in expansive arrays of non-volatile memory devices, known as resistive processing units (RPUs). These RPUs facilitate massively parallel matrix operations, leading to significant enhancements in both performance and energy efficiency. Electrochemical random-access memory (ECRAM), leveraging ion dynamics in secondary-ion battery materials, has emerged as a promising candidate for RPUs. ECRAM achieves over 1000 memory states through precise ion movement control, prompting early-stage research into material stacks such as mobile ion species and electrolyte materials. Crucially, the analog states in ECRAMs update symmetrically with pulse number (or voltage polarity), contributing to high network performance. Recent strides in device engineering in planar and three-dimensional structures and the understanding of ECRAM operation physics have marked significant progress in a short research period. This paper aims to review ECRAM material advancements through literature surveys, offering a systematic discussion on engineering assessments for ion control and a physical understanding of array-level demonstrations. Finally, the review outlines future directions for improvements, co-optimization, and multidisciplinary collaboration in circuits, algorithms, and applications to develop energy-efficient, next-generation AI hardware systems.
ABSTRACT
Memristors offer a promising solution to address the performance and energy challenges faced by conventional von Neumann computer systems. Yet, stochastic ion migration in conductive filament often leads to an undesired performance tradeoff between memory window, retention, and endurance. Herein, a robust memristor based on oxygen-rich SnO2 nanoflowers switching medium, enabled by seed-mediated wet chemistry, to overcome the ion migration issue for enhanced analog in-memory computing is reported. Notably, the interplay between the oxygen vacancy (Vo) and Ag ions (Ag+) in the Ag/SnO2/p++-Si memristor can efficiently modulate the formation and abruption of conductive filaments, thereby resulting in a high on/off ratio (>106), long memory retention (10-year extrapolation), and low switching variability (SV = 6.85%). Multiple synaptic functions, such as paired-pulse facilitation, long-term potentiation/depression, and spike-time dependent plasticity, are demonstrated. Finally, facilitated by the symmetric analog weight updating and multiple conductance states, a high image recognition accuracy of ≥ 91.39% is achieved, substantiating its feasibility for analog in-memory computing. This study highlights the significance of synergistically modulating conductive filaments in optimizing performance trade-offs, balancing memory window, retention, and endurance, which demonstrates techniques for regulating ion migration, rendering them a promising approach for enabling cutting-edge neuromorphic applications.
ABSTRACT
A neuromorphic system is composed of hardware-based artificial neurons and synaptic devices, designed to improve the efficiency of neural computations inspired by energy-efficient and parallel operations of the biological nervous system. A synaptic device-based array can compute vector-matrix multiplication (VMM) with given input voltage signals, as a non-volatile memory device stores the weight information of the neural network in the form of conductance or capacitance. However, unlike software-based neural networks, the neuromorphic system unavoidably exhibits non-ideal characteristics that can have an adverse impact on overall system performance. In this study, the characteristics required for synaptic devices and their importance are discussed, depending on the targeted application. We categorize synaptic devices into two types: conductance-based and capacitance-based, and thoroughly explore the operations and characteristics of each device. The array structure according to the device structure and the VMM operation mechanism of each structure are analyzed, including recent advances in array-level implementation of synaptic devices. Furthermore, we reviewed studies to minimize the effect of hardware non-idealities, which degrades the performance of hardware neural networks. These studies introduce techniques in hardware and signal engineering, as well as software-hardware co-optimization, to address these non-idealities through compensation approaches.
ABSTRACT
The photovoltaic effect is gaining growing attention in the optoelectronics field due to its low power consumption, sustainable nature, and high efficiency. However, the photovoltaic effects hitherto reported are hindered by the stringent band-alignment requirement or inversion symmetry-breaking, and are challenging for achieving multifunctional photovoltaic properties (such as reconfiguration, nonvolatility, and so on). Here, a novel ionic photovoltaic effect in centrosymmetric CdSb2Se3Br2 that can overcome these limitations is demonstrated. The photovoltaic effect displays significant anisotropy, with the photocurrent being most apparent along the CdBr2 chains while absent perpendicular to them. Additionally, the device shows electrically-induced nonvolatile photocurrent switching characteristics. The photovoltaic effect is attributed to the modulation of the built-in electric field through the migration of Br ions. Using these unique photovoltaic properties, a highly secure circuit with electrical and optical keys is successfully implemented. The findings not only broaden the understanding of the photovoltaic mechanism, but also provide a new material platform for the development of in-memory sensing and computing devices.