Ambipolar Barristors for Reconfigurable Logic Circuits.

Vertical heterostructures based on graphene have emerged as a unique architecture for novel electronic devices with unusual characteristics. Here we report a new design of vertical ambipolar barristors based on metal-graphene-silicon-graphene sandwich structure, using the bottom graphene as a gate-tunable "active contact", the top graphene as an adaptable Ohmic contact, and the low doping thin silicon layer as the switchable channel. Importantly, with finite density of states and weak screening effect of graphene, we demonstrate, for the first time, that both the carrier concentration and majority carrier type in the sandwiched silicon can be readily modulated by gate potential penetrating through graphene. It can thus enable a new type of ambipolar barristors with an ON-OFF ratio exceeding 103. Significantly, these ambipolar barristors can be flexibly configured into either p-type or n-type transistors and used to create integrated circuits with reconfigurable logic functions. This unconventional device structure and ambipolar reconfigurable characteristics can open up exciting opportunities in future electronics based on graphene or two-dimensional van der Waals heterostructures.

Vertical Ge/Si Core/Shell Nanowire Junctionless Transistor.

Vertical junctionless transistors with a gate-all-around (GAA) structure based on Ge/Si core/shell nanowires epitaxially grown and integrated on a ⟨111⟩ Si substrate were fabricated and analyzed. Because of efficient gate coupling in the nanowire-GAA transistor structure and the high density one-dimensional hole gas formed in the Ge nanowire core, excellent P-type transistor behaviors with Ion of 750 µA/µm were obtained at a moderate gate length of 544 nm with minimal short-channel effects. The experimental data can be quantitatively modeled by a GAA junctionless transistor model with few fitting parameters, suggesting the nanowire transistors can be fabricated reliably without introducing additional factors that can degrade device performance. Devices with different gate lengths were readily obtained by tuning the thickness of an etching mask film. Analysis of the histogram of different devices yielded a single dominate peak in device parameter distribution, indicating excellent uniformity and high confidence of single nanowire operation. Using two vertical nanowire junctionless transistors, a PMOS-logic inverter with near rail-to-rail output voltage was demonstrated, and device matching in the logic can be conveniently obtained by controlling the number of nanowires employed in different devices rather than modifying device geometry. These studies show that junctionless transistors based on vertical Ge/Si core/shell nanowires can be fabricated in a controlled fashion with excellent performance and may be used in future hybrid, high-performance circuits where bottom-up grown nanowire devices with different functionalities can be directly integrated with an existing Si platform.

A 2D Optoelectronic Logic Device with Ultralow Supply Voltage.

Optoelectronic logic devices (OELDs) provide a cure for many visually impaired individuals. However, traditional OELDs have limitations, such as excessive channel resistance and complex structure, leading to high supply voltage and decreased efficiency of signal transmission. We report ultralow-voltage OELDs by seriating two 2D MoTe2 transistors with sub-10 nm channel lengths. The short channel length and atomically flat interface result in a low-resistance light-sensing unit that can operate with a low supply voltage and function well in weak-light conditions. The devices achieve an on state without light signal input and an off state with light signal input at an ultralow supply voltage of 50 mV, lower than the retinal bearing voltage of 70 mV. Additionally, MoTe2's excellent optoelectronic properties allow the device to perceive light from visible to near-infrared wavelengths with high sensitivity to weak light signals. The specific perception of visible light intensity is 0.03 mW·mm-2, and the near-infrared light intensity is 0.1 mW mm-2. The device also has a response time of 8 ms, meeting human needs. Our findings provide a promising solution for developing low-voltage artificial retinas.

InP Crystal Phase Heterojunction Transistor with a Vertical Gate-All-Around Structure.

Crystal phase transitions can form a new type of heterojunction with different atomic arrangements in the same material: crystal phase heterojunction (CPHJ). The CPHJ has an inherently strong impact on band engineering without concerns over critical thicknesses with misfit dislocations and a semiconductor-metal transition. In-plane CPHJ was recently demonstrated in two-dimensional (2D) transition-metal dichalcogenide (TMD) materials and utilized for conventional planar field-effect transistor applications. However, scalability such as gate electrostatic control, miniaturization, and multigate structure have been limited because of the geometrical issue. Here, we demonstrated a transistor using the CPHJ with a vertical gate-all-around structure by forming a CPHJ in conventional III-V semiconductors. The CPHJ, composed of wurtzite InP nanowires with zincblende InP substrates, showed an atomically flat heterojunction without dislocations and indicated a Type-II band discontinuity across the junction. The CPHJ transistor had moderate to good gate electrostatic controllability with high on-state currents and transconductance. The CPHJ offer will provide a new switching mechanism and add a new junction and device design choice to the long history of transistors.

Reconfigurable Vertical Phototransistor with MoTe2 Homojunction for High-Speed Rectifier and Multivalued Logical Circuits.

The most reported two-dimensional (2D) reconfigurable multivalued logic (RMVL) devices primarily involve a planar configuration and carrier transport, which limits the high-density circuit integration and high-speed logic operation. In this work, the vertical transistors with reconfigurable MoTe2 homojunction are developed for low-power, high-speed, multivalued logic circuits. Through top/bottom dual-gate modulation, the transistors can be configured into four modes: P-i-N, N-i-P, P-i-P, and N-i-N. The reconfigurable rectifying and photovoltaic behaviors are observed in P-i-N and N-i-P configurations, exhibiting ideal diode characteristics with a current rectification ratio over 105 and sign-reversible photovoltaic response with a photoswitching ratio up to 7.44 × 105. Taking advantage of the seamless homogeneous integration and short vertical channel architecture, the transistor can operate as an electrical switch with an ultrafast speed of 680 ns, surpassing the conventional p-n diode. The MoTe2 half-wave rectifier is then applied in high-frequency integrated circuits using both square wave and sinusoidal waveforms. By applying an electrical pulse with a 1/4 phase difference between two input signals, the RMVL circuit has been achieved. This work proposes a universal and reconfigurable vertical transistor, enabled by dual-gate electrostatic doping on top/bottom sides of MoTe2 homojunction, suggesting a high integration device scheme for high-speed RMVL circuits and systems.

GaN Vertical Transistors with Staircase Channels for High-Voltage Applications.

In this study, we propose and simulate the design of a non-regrowth staircase channel GaN vertical trench transistor, demonstrating an exceptional threshold and breakdown characteristic for high power and high frequency applications. The unique staircase design provides a variable capacitance through the gate-dielectric-semiconductor interface, which results in a high breakdown voltage of 1.52 kV and maintains a channel on-resistance of 2.61 mΩ∙cm2. Because of the variable length and doping profile in the channel region, this model offers greater flexibility to meet a wide range of device application requirements.

High-Frequency Operation of Vertical Organic Field-Effect Transistors.

The high-frequency and low-voltage operation of organic thin-film transistors (OTFTs) is a key requirement for the commercial success of flexible electronics. Significant progress has been achieved in this regard by several research groups highlighting the potential of OTFTs to operate at several tens or even above 100 MHz. However, technology maturity, including scalability, integrability, and device reliability, is another crucial point for the semiconductor industry to bring OTFT-based flexible electronics into mass production. These requirements are often not met by high-frequency OTFTs reported in the literature as unconventional processes, such as shadow-mask patterning or alignment with unrealistic tolerances for production, are used. Here, ultra-short channel vertical organic field-effect transistors (VOFETs) with a unity current gain cut-off frequency (fT ) up to 43.2 MHz (or 4.4 MHz V-1 ) operating below 10 V are shown. Using state-of-the-art manufacturing techniques such as photolithography with reliable fabrication procedures, the integration of such devices down to the size of only 12 × 6 µm2 is shown, which is important for the adaption of this technology in high-density circuits (e.g., display driving). The intrinsic channel transconductance is analyzed and demonstrates that the frequencies up to 430 MHz can be reached if the parasitic electrode overlap is minimized.

All-Inkjet-Printed Vertical Heterostructure for Wafer-Scale Electronics.

In this study, we fabricated an array of all-inkjet-printed vertical Schottky barrier (SB) transistors and various logic gates on a large-area substrate. All of the electronic components, including the indium-gallium-zinc-oxide (IGZO) semiconductor, reduced graphene oxide (rGO), and indium-tin-oxide (ITO) electrodes, and the ion-gel gate dielectric, were directly and uniformly printed onto a 4 in. wafer. The vertical SB transistors had a vertically stacked structure, with the inkjet-printed IGZO semiconductor layer placed between the rGO source electrode and the ITO drain electrode. The ion-gel gate dielectric was also inkjet-printed in a coplanar gate geometry. The channel current was controlled by adjusting the SB height at the rGO/IGZO heterojunction under application of an external gate voltage. The high intrinsic capacitance of the ion-gel gate dielectric facilitated modulation of the SB height at the source/channel heterojunction to around 0.5 eV at a gate voltage lower than 2 V. The resulting vertical SB transistors exhibited a high current density of 2.0 A·cm-2, a high on-off current ratio of 106, and excellent operational and environmental stabilities. The simple device structure of the vertical SB transistors was beneficial for the fabrication of all-inkjet-printed low-power logic circuits such as the NOT, NAND, and NOR gates on a large-area substrate.

Vertically Stacked CVD-Grown 2D Heterostructure for Wafer-Scale Electronics.

This paper demonstrates, for the first time, wafer-scale graphene/MoS2 heterostructures prepared by chemical vapor deposition (CVD) and their application in vertical transistors and logic gates. A CVD-grown bulk MoS2 layer is utilized as the vertical channel, whereas CVD-grown monolayer graphene is used as the tunable work-function electrode. The short vertical channel of the transistor is formed by sandwiching bulk MoS2 between the bottom indium tin oxide (ITO, drain electrode) and the top graphene (source electrode). The electron injection barriers at the graphene-MoS2 junction and ITO-MoS2 junction are modulated effectively through variation of the Schottky barrier height and its effective barrier width, respectively, because of the work-function tunability of the graphene electrode. The resulting vertical transistor with the CVD-grown MoS2/graphene heterostructure exhibits a current density exceeding 7 A/cm2, a subthreshold swing of 410 mV/dec, and an on-off current ratio exceeding 103. The large-area synthesis, transfer, and patterning processes of both semiconducting MoS2 and metallic graphene facilitate construction of a wafer-scale array of transistors and logic gates such as NOT, NAND, and NOR.

Maximizing the Current Output in Self-Aligned Graphene-InAs-Metal Vertical Transistors.

With finite density of states and electrostatically tunable work function, graphene can function as a tunable contact for a semiconductor channel to enable vertical field-effect transistors (VFETs). However, the overall performance, especially the output current density, is still limited by the low conductance of the vertical semiconductor channel, as well as large series resistance of the graphene electrode. To overcome these limitations, we construct a VFET by using single-crystal InAs film as the high-conductance vertical channel and self-aligned metal contact as the source-drain electrodes, resulting in a record high current density over 45 000 A/cm2 at a low bias voltage of 1 V. Furthermore, we construct a device-level VFET model using the resistor network method, and experimentally validate the impact of each geometry parameter on device performance. Importantly, we found the device performance is not only a function of the intrinsic channel material, but also greatly influenced by device geometries and footprint. Our study not only pushes the performance limit of graphene VFETs, but also sheds light on van der Waals integration between two-dimensional material and conventional bulk material for high-performance VFETs and circuits.

High-Performance Thin-Film Transistors of Quaternary Indium-Zinc-Tin Oxide Films Grown by Atomic Layer Deposition.

A new deposition technique is required to grow the active oxide semiconductor layer for emerging oxide electronics beyond the conventional sputtering technique. Atomic layer deposition (ALD) has the benefits of versatile composition control, low defect density in films, and conformal growth over a complex structure, which can hardly be obtained with sputtering. This study demonstrates the feasibility of growing amorphous In-Zn-Sn-O (a-IZTO) through ALD for oxide thin-film transistor (TFT) applications. In the ALD of the a-IZTO film, the growth behavior indicates that there exists a growth correlation between the precursor molecules and the film surface where the ALD reaction occurs. This provides a detailed understanding of the ALD process that is required for precise composition control. The a-IZTO film with In/Zn/Sn = 10:70:20 was chosen for high-performance TFTs, among other compositions, regarding the field-effect mobility (µFE), turn-on voltage ( Von), and subthreshold swing (SS) voltage. The optimized TFT device with the a-IZTO film thickness of 8 nm revealed a high performance with a µFE of 22 cm2 V-1 s-1, Von of 0.8 V, and SS of 0.15 V dec-1 after annealing at 400 °C for 30 min. Furthermore, an emerging device such as a vertical channel TFT was demonstrated. Thus, the a-IZTO ALD process could offer promising opportunities for a variety of emerging oxide electronics beyond planar TFTs.

Vertical Field Emission Air-Channel Diodes and Transistors.

Vacuum channel transistors are potential candidates for low-loss and high-speed electronic devices beyond complementary metal-oxide-semiconductors (CMOS). When the nanoscale transport distance is smaller than the mean free path (MFP) in atmospheric pressure, a transistor can work in air owing to the immunity of carrier collision. The nature of a vacuum channel allows devices to function in a high-temperature radiation environment. This research intended to investigate gate location in a vertical vacuum channel transistor. The influence of scattering under different ambient pressure levels was evaluated using a transport distance of about 60 nm, around the range of MFP in air. The finite element model suggests that gate electrodes should be near emitters in vertical vacuum channel transistors because the electrodes exhibit high-drive currents and low-subthreshold swings. The particle trajectory model indicates that collected electron flow (electric current) performs like a typical metal oxide semiconductor field effect-transistor (MOSFET), and that gate voltage plays a role in enhancing emission electrons. The results of the measurement on vertical diodes show that current and voltage under reduced pressure and filled with CO2 are different from those under atmospheric pressure. This result implies that this design can be used for gas and pressure sensing.

Inkjet-Printed Vertical Organic Field-Effect Transistor Arrays and Their Image Sensors.

Vertical organic field-effect transistors (VOFETs) have been explored with a higher current density, a faster switch speed, and a better air stability than conventional OFETs, which dramatically enhance the capability of driving an AMOLED backplane. Unfortunately, the state-of-the-art of the fabrication of solution-processed VOFETs is still very complicated, which can only focus at a single-cell level. In this work, with the assistance of the inkjet print, the fabrication process of a solution-processed VOFET was significantly simplified, and a solution-processed VOFET array was fabricated for the first time, which exhibited excellent device performance and outstanding mechanical stability. More importantly, the VOFET arrays exhibited excellent photodetector properties, and a flexible image sensor based on VOFET arrays with multipoint visible photodetection and image recognition was demonstrated for the first time. Therefore, this novel process dramatically simplified the VOFET device fabrication process and a successfully realized array, which promoted the commercialization of VOFET and showed great potential in flexible display, multifunctional sensors, and wearable integrated circuits.

Advanced Organic Permeable-Base Transistor with Superior Performance.

An optimized vertical organic permeable-base transistor (OPBT) competing with the best organic field-effect transistors in performance, while employing low-cost fabrication techniques, is presented. The OPBT stands out by its excellent power efficiency at the highest frequencies.