Study on the Expression Significance of Mb, BChE and cTnI in Myocardial Infarction and Their Relationship with Prognosis.

Objective: Circulating biomarkers can be used as effective prediction tools for AMI diagnosis and prognosis, but their prediction efficiency is limited and still needs to be explored. The study aimed to investigate the changes of myocardial troponin I (cTn I), myoglobin (Mb), and butyryl cholinesterase (BChE) levels in patients with acute myocardial infarction (AMI) and its clinical predictive efficacy. Methods: In this prospective cohort study, fifty patients with AMI who received PCI (AMI group) and 50 healthy subjects who underwent physical examination (reference group) during the same period were included. According to the occurrence of short-term major adverse cardiovascular events (MACE) during 6-month follow-up, they were divided into MACE group and non-MACE group . The difference of Mb, BChE, and cTnI levels was compared, and the ROC curve was drawn to analyze the prediction efficiency. Results: Compared with the reference group or non-MACE group, Mb and cTnI significantly increased and BChE significantly decreased inAMI group and MACE group, respectively (P < .05). The AUC of Mb, cTnI and BChE in diagnosing AMI occurrence and prognosis were all > 0.75, and the sensitivity and specificity were all > 85.00%. cTnI, Mb and BChE have good diagnostic efficacy in disease occurrence and prognosis evaluation of AMI patients. Conclusions: High expression of Mb and cTnI and low expression of BChE can increase the risk of AMI incidence and MACE occurrence and have high diagnostic efficacy, which can be used as sensitive factors in clinical AMI diagnosis and evaluation. Thess provided a theoretical foundation for AMI diagnosis and MACE preventing in AMI patients.

Strengthened Complementary Metal-Oxide-Semiconductor Logic for Small-Band-Gap Semiconductor-Based High-Performance and Low-Power Application.

Silicon-based complementary metal-oxide-semiconductor (CMOS) has been the mainstream logic style for modern digital integrated circuits (ICs) for decades but will meet its performance limits soon. Extensive investigations have thus been carried out using other semiconductors, especially those with extremely high carrier mobility. However, these materials usually have small or even zero band gap, which leads inevitably to large leakage current or voltage loss in ICs based on these semiconductors. In this work, we propose and demonstrate a strengthened CMOS (SCMOS) logic style using modified field-effect transistors (FETs) to solve this problem, that is, to achieve high performance, utilizing the high carrier mobility in these materials, and to reduce the current leakage resulting from their small band gap. Conventional CMOS FETs are modified to have an asymmetric structure where an additional assistant gate is introduced near the drain to further lower the potential barrier in on-state and to increase the barrier in off-state. SCMOS ICs are constructed using these modified asymmetric CMOS FETs, which demonstrate perfect rail-to-rail output with negligible voltage loss and 3 orders of magnitude suppression of the static power consumption and an operating speed similar to or even higher than that of CMOS ICs. Here, SCMOS is demonstrated using carbon nanotubes, but, in principle, this logic style can be used in ICs based on any small-band-gap semiconductors to provide simultaneously high performance and low power consumption.

Scaling carbon nanotube complementary transistors to 5-nm gate lengths.

High-performance top-gated carbon nanotube field-effect transistors (CNT FETs) with a gate length of 5 nanometers can be fabricated that perform better than silicon complementary metal-oxide semiconductor (CMOS) FETs at the same scale. A scaling trend study revealed that the scaled CNT-based devices, which use graphene contacts, can operate much faster and at much lower supply voltage (0.4 versus 0.7 volts) and with much smaller subthreshold slope (typically 73 millivolts per decade). The 5-nanometer CNT FETs approached the quantum limit of FETs by using only one electron per switching operation. In addition, the contact length of the CNT CMOS devices was also scaled down to 25 nanometers, and a CMOS inverter with a total pitch size of 240 nanometers was also demonstrated.