Modern microprocessor built from complementary carbon nanotube transistors.

Electronics is approaching a major paradigm shift because silicon transistor scaling no longer yields historical energy-efficiency benefits, spurring research towards beyond-silicon nanotechnologies. In particular, carbon nanotube field-effect transistor (CNFET)-based digital circuits promise substantial energy-efficiency benefits, but the inability to perfectly control intrinsic nanoscale defects and variability in carbon nanotubes has precluded the realization of very-large-scale integrated systems. Here we overcome these challenges to demonstrate a beyond-silicon microprocessor built entirely from CNFETs. This 16-bit microprocessor is based on the RISC-V instruction set, runs standard 32-bit instructions on 16-bit data and addresses, comprises more than 14,000 complementary metal-oxide-semiconductor CNFETs and is designed and fabricated using industry-standard design flows and processes. We propose a manufacturing methodology for carbon nanotubes, a set of combined processing and design techniques for overcoming nanoscale imperfections at macroscopic scales across full wafer substrates. This work experimentally validates a promising path towards practical beyond-silicon electronic systems.

Tunable n-Type Doping of Carbon Nanotubes through Engineered Atomic Layer Deposition HfOX Films.

Although digital systems fabricated from carbon-nanotube-based field-effect transistors (CNFETs) promise significant energy efficiency benefits, realizing these benefits requires a complementary CNFET technology, i.e., CNFET CMOS, comprising both PMOS and NMOS CNFETs. Furthermore, this CNFET CMOS process must be robust ( e.g., air-stable), tunable ( e.g., ability to control CNFET threshold voltages), and silicon CMOS compatible (to integrate within existing manufacturing facilities and process flows). Despite many efforts, such a silicon CMOS compatible CNT doping strategy for forming NMOS CNFETs does not exist. Techniques today are either not air-stable (using reactive low work function metals), not solid-state or silicon CMOS compatible (employing soluble molecular dopants in ionic solutions), or have not demonstrated precise control over the amount of doping (for setting threshold voltage,  VT). Here, we demonstrate an electrostatic doping technique that meets all of these requirements. The key to our technique is leveraging atomic layer deposition (ALD) to encapsulate CNTs with nonstoichiometric oxides. We show that ALD allows for precise control of oxide stoichiometry, which translates to direct control of the amount of CNT doping. We experimentally demonstrate the ability to modulate the strength of the p-type conduction branch by >2500× (measured as the change in current at fixed bias), realize NMOS CNFETs with n-type conduction ∼500× stronger than p-type conduction (also measured by the relative current at fixed biases), and tune VT over a ∼1.5 V range. Moreover, our technique is compatible with other doping schemes; as an illustration, we combine electrostatic doping and low work function contact engineering to achieve CNFET CMOS with symmetric NMOS and PMOS ( i.e., CNFET ON-current for NMOS and PMOS is within 6% of each other). Thus, this work realizes a solid-state, air-table, very large scale integration and silicon CMOS compatible doping strategy, enabling integration of CNFET CMOS within standard fabrication processes today.