Hybrid neuromorphic hardware with sparing 2D synapse and CMOS neuron for character recognition.

Neuromorphic computing enables efficient processing of data-intensive tasks, but requires numerous artificial synapses and neurons for certain functions, which leads to bulky systems and energy challenges. Achieving functionality with fewer synapses and neurons will facilitate integration density and computility. Two-dimensional (2D) materials exhibit potential for artificial synapses, including diverse biomimetic plasticity and efficient computing. Considering the complexity of neuron circuits and the maturity of complementary metal-oxide-semiconductor (CMOS), hybrid integration is attractive. Here, we demonstrate a hybrid neuromorphic hardware with 2D MoS2 synaptic arrays and CMOS neural circuitry integrated on board. With the joint benefit of hybrid integration, frequency coding and feature extraction, a total cost of twelve MoS2 synapses, three CMOS neurons, combined with digital/analogue converter enables alphabetic and numeric recognition. MoS2 synapses exhibit progressively tunable weight plasticity, CMOS neurons integrate and fire frequency-encoded spikes to display the target characters. The synapse- and neuron-saving hybrid hardware exhibits a competitive accuracy of 98.8% and single recognition energy consumption of 11.4 µW. This work provides a viable solution for building neuromorphic hardware with high compactness and computility.

Pass-Transistor Logic Circuits Based on Wafer-Scale 2D Semiconductors.

2D semiconductors, such as molybdenum disulfide (MoS2 ), have attracted tremendous attention in constructing advanced monolithic integrated circuits (ICs) for future flexible and energy-efficient electronics. However, the development of large-scale ICs based on 2D materials is still in its early stage, mainly due to the non-uniformity of the individual devices and little investigation of device and circuit-level optimization. Herein, a 4-inch high-quality monolayer MoS2 film is successfully synthesized, which is then used to fabricate top-gated (TG) MoS2 field-effect transistors with wafer-scale uniformity. Some basic circuits such as static random access memory and ring oscillators are examined. A pass-transistor logic configuration based on pseudo-NMOS is then employed to design more complex MoS2 logic circuits, which are successfully fabricated with proper logic functions tested. These preliminary integration efforts show the promising potential of wafer-scale 2D semiconductors for application in complex ICs.