Silicon Waveguide-Integrated Carbon Nanotube Photodetector with Low Dark Current and 48 GHz Bandwidth.

Low-dimensional materials with excellent optoelectronic properties and complementary metal-oxide-semiconductor (CMOS) process compatibility have the potential to construct high-performance photodetectors used in a cost-efficient monolithic or hybrid integrated optical communication system. Carbon nanotubes (CNTs) have attracted a lot of attention due to special geometric structure and broad band response, high optical absorption coefficient, ps-level intrinsic light response, high carrier mobility and wafer-scaled production process. Here, we demonstrated a high-performance waveguide-integrated CNT photodetector with asymmetric palladium (Pd) and hafnium (Hf) contact electrodes. The ideal photodetector structure was realized via comparing with simulation and experimental results, where the optimized device achieved a high 3 dB bandwidth ∼48 GHz at 0 V, as well as a responsivity ∼73.62 mA/W and dark current ∼0.157 µA at -2 V bias voltage. This waveguide-integrated CNT photodetector with low dark current and high bandwidth is helpful for next-generation optical communication and high-speed optical interconnects.

Ultrasensitive Magnetic Sensors Enabled by Heterogeneous Integration of Graphene Hall Elements and Silicon Processing Circuits.

Graphene Hall elements (GHEs) have been demonstrated to be promising magnetic field sensors with excellent sensitivity, linearity, temperature stability, and compatibility with complementary-metal-oxide-semiconductor (CMOS)-integrated circuits (ICs). However, the demonstrated GHEs have still not exhibited a comprehensive advantage in performance over commercial integrated Hall sensors which were implemented in integrated Hall element and CMOS processing ICs. In this work, we develop a technology for the three-dimensional (3D) heterogeneous integration of silicon-based CMOS ICs and GHEs, and the fabricated magnetic field sensors outperform commercial high-end integrated Hall sensors. Specifically, the integrated Hall sensors are implemented in a stacked integration on Si based on a chopper programmable-gain amplifier (CPGA), a chopper-stabilized second-order sigma-delta modulator (CSDM), and graphene-based Hall elements on monochips. GHEs with high sensitivity (up to 1000 A/VT) are fabricated with a compatible process on a smoothened silicon nitride passivation layer of silicon-based CMOS ICs, and the two device layers are connected by an interlayer. The heterogeneous integrated Hall ICs exhibit current and voltage magnetic sensitivities up to 64 000 A/VT and 6.12 V/VT, respectively, which are much higher than those in all other reported nanomaterial-based Hall sensors and even in high-end commercial Hall ICs. Furthermore, the 3D heterogeneous integration technology used here can be extended as a universal technology for integrating nanomaterial-based sensors and Si CMOS ICs.

Strengthened Complementary Metal-Oxide-Semiconductor Logic for Small-Band-Gap Semiconductor-Based High-Performance and Low-Power Application.

Silicon-based complementary metal-oxide-semiconductor (CMOS) has been the mainstream logic style for modern digital integrated circuits (ICs) for decades but will meet its performance limits soon. Extensive investigations have thus been carried out using other semiconductors, especially those with extremely high carrier mobility. However, these materials usually have small or even zero band gap, which leads inevitably to large leakage current or voltage loss in ICs based on these semiconductors. In this work, we propose and demonstrate a strengthened CMOS (SCMOS) logic style using modified field-effect transistors (FETs) to solve this problem, that is, to achieve high performance, utilizing the high carrier mobility in these materials, and to reduce the current leakage resulting from their small band gap. Conventional CMOS FETs are modified to have an asymmetric structure where an additional assistant gate is introduced near the drain to further lower the potential barrier in on-state and to increase the barrier in off-state. SCMOS ICs are constructed using these modified asymmetric CMOS FETs, which demonstrate perfect rail-to-rail output with negligible voltage loss and 3 orders of magnitude suppression of the static power consumption and an operating speed similar to or even higher than that of CMOS ICs. Here, SCMOS is demonstrated using carbon nanotubes, but, in principle, this logic style can be used in ICs based on any small-band-gap semiconductors to provide simultaneously high performance and low power consumption.

Scaling carbon nanotube complementary transistors to 5-nm gate lengths.

High-performance top-gated carbon nanotube field-effect transistors (CNT FETs) with a gate length of 5 nanometers can be fabricated that perform better than silicon complementary metal-oxide semiconductor (CMOS) FETs at the same scale. A scaling trend study revealed that the scaled CNT-based devices, which use graphene contacts, can operate much faster and at much lower supply voltage (0.4 versus 0.7 volts) and with much smaller subthreshold slope (typically 73 millivolts per decade). The 5-nanometer CNT FETs approached the quantum limit of FETs by using only one electron per switching operation. In addition, the contact length of the CNT CMOS devices was also scaled down to 25 nanometers, and a CMOS inverter with a total pitch size of 240 nanometers was also demonstrated.

CMOS-based carbon nanotube pass-transistor logic integrated circuits.

Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration.