Device-Algorithm Co-Optimization for an On-Chip Trainable Capacitor-Based Synaptic Device with IGZO TFT and Retention-Centric Tiki-Taka Algorithm.

Analog in-memory computing synaptic devices are widely studied for efficient implementation of deep learning. However, synaptic devices based on resistive memory have difficulties implementing on-chip training due to the lack of means to control the amount of resistance change and large device variations. To overcome these shortcomings, silicon complementary metal-oxide semiconductor (Si-CMOS) and capacitor-based charge storage synapses are proposed, but it is difficult to obtain sufficient retention time due to Si-CMOS leakage currents, resulting in a deterioration of training accuracy. Here, a novel 6T1C synaptic device using only n-type indium gaIlium zinc oxide thin film transistor (IGZO TFT) with low leakage current and a capacitor is proposed, allowing not only linear and symmetric weight update but also sufficient retention time and parallel on-chip training operations. In addition, an efficient and realistic training algorithm to compensate for any remaining device non-idealities such as drifting references and long-term retention loss is proposed, demonstrating the importance of device-algorithm co-optimization.

Exchange-induced electron transport in heavily phosphorus-doped si nanowires.

Heavily phosphorus-doped silicon nanowires (Si NWs) show intriguing transport phenomena at low temperature. As we decrease the temperature, the resistivity of the Si NWs initially decreases, like metals, and starts to increase logarithmically below a resistivity minimum temperature (T(min)), which is accompanied by (i) a zero-bias dip in the differential conductance and (ii) anisotropic negative magnetoresistance (MR), depending on the angle between the applied magnetic field and current flow. These results are associated with the impurity band conduction and electron scattering by the localized spins at phosphorus donor states. The analysis on the MR reveals that the localized spins are coupled antiferromagnetically at low temperature via the exchange interaction.

Large-scale assembly of highly flexible low-noise devices based on silicon nanowires.

Recently, integrated flexible devices based on silicon nanowires (Si-NWs) have received significant attention as high performance flexible devices. However, most previous assembly methods can generate only specifically-shaped devices and require unconventional facilities, which has been a major hurdle for industrial applications. Herein, we report a simple but very efficient method for assembling Si-NWs into virtually generally-shape patterns on flexible substrates using only conventional microfabrication facilities, allowing us to mass-produce highly flexible low-noise devices. As proof of this method, we demonstrated the fabrication of highly bendable top-gate transistors based on Si-NWs. These devices showed typical n-type semiconductor behaviors, and exhibited a much lower noise level compared to previous flexible devices based on organic conductors or other nanowires. In addition, the gating behaviors and low-noise characteristics of our devices were maintained, even under highly bent conditions.